NLV74VHC74DTR2G

Obsolete

ON Semiconductor

DUAL D FLIP-FLOP WITH SET AND RESET

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DocumentsPackage Drawing-948G-TSSOP-14 WB Datasheet

Integrated Circuits (ICs)

NLV74VHC74DTR2G

Obsolete

ON Semiconductor

DUAL D FLIP-FLOP WITH SET AND RESET

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DocumentsPackage Drawing-948G-TSSOP-14 WB Datasheet

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	NLV74VHC74DTR2G

Clock Frequency	115 MHz
Current - Output High, Low [custom]	8 mA
Current - Output High, Low [custom]	8 mA
Current - Quiescent (Iq)	2 µA
Function	Reset, Set(Preset)
Grade	Automotive
Input Capacitance	4 pF
Max Propagation Delay @ V, Max CL	9.3 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Complementary
Package / Case	14-TSSOP
Package / Case [custom]	0.173 "
Package / Case [custom]	4.4 mm
Qualification	AEC-Q100
Supplier Device Package	14-TSSOP
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	2 V

MC74VHC74 Series

Dual D Flip-Flop with Set and Reset

Part	Current - Quiescent (Iq)	Package / Case [x]	Package / Case [y]	Package / Case	Function	Number of Elements	Max Propagation Delay @ V, Max CL	Output Type	Number of Bits per Element	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Mounting Type	Trigger Type	Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Clock Frequency	Input Capacitance	Supplier Device Package	Package / Case [custom]	Package / Case [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Grade	Qualification
ON Semiconductor 74VHC74MX	2 µA	0.154 in	3.9 mm	14-SOIC	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA	85 °C	-40 °C	Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF
ON Semiconductor 74VHC74MTCX	2 µA			14-TSSOP	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA	85 °C	-40 °C	Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF	14-TSSOP	0.173 "	4.4 mm
ON Semiconductor 74VHC74SJX	2 µA	0.209 "	5.3 mm	14-SOIC	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA	85 °C	-40 °C	Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF	14-SOP
ON Semiconductor 74VHC74M	2 µA	0.154 in	3.9 mm	14-SOIC	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA	85 °C	-40 °C	Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF
ON Semiconductor MC74VHC74D	2 µA	0.154 in	3.9 mm	14-SOIC	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA			Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF				125 °C	-55 °C
ON Semiconductor NLV74VHC74DTR2G	2 µA			14-TSSOP	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA			Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF	14-TSSOP	0.173 "	4.4 mm	125 °C	-55 °C	Automotive	AEC-Q100
ON Semiconductor 74VHC74MTC	2 µA			14-TSSOP	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA	85 °C	-40 °C	Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF	14-TSSOP	0.173 "	4.4 mm
ON Semiconductor MC74VHC74ML1
ON Semiconductor MC74VHC74DT	2 µA			14-TSSOP	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA			Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF	14-TSSOP	0.173 "	4.4 mm	125 °C	-55 °C
ON Semiconductor 74VHC74MX	2 µA	0.154 in	3.9 mm	14-SOIC	Reset Set(Preset)	2	9.3 ns	Complementary	1	8 mA	8 mA	85 °C	-40 °C	Surface Mount	Positive Edge	D-Type	5.5 V	2 V	115 MHz	4 pF

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.64
		10	$ 0.56
		25	$ 0.53
		100	$ 0.40
		250	$ 0.34
		500	$ 0.32
		1000	$ 0.25
	Digi-Reel®	1	$ 0.64
		10	$ 0.56
		25	$ 0.53
		100	$ 0.40
		250	$ 0.34
		500	$ 0.32
		1000	$ 0.25
	Tape & Reel (TR)	2500	$ 0.23
		5000	$ 0.22
		12500	$ 0.21
		25000	$ 0.21

Description

General part information

MC74VHC74 Series

The MC74VHC74 is an advanced high speed CMOS D-type flip-flop fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.The signal level applied to the D input is transferred to Q output during the positive going transition of the Clock pulse.Reset (RD) and Set (SD) are independent of the Clock (CP) and are accomplished by setting the appropriate input Low.The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.