Deep-Dive with AI
Search across all available documentation for this part.
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CD4532BF3A |
|---|---|
| Circuit [custom] | 3 |
| Circuit [custom] | 8 |
| Circuit [custom] | 1 |
| Current - Output High, Low [custom] | 6.8 mA |
| Current - Output High, Low [custom] | 6.8 mA |
| Independent Circuits | 1 |
| Mounting Type | Through Hole |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 7.62 mm, 0.3 in |
| Package / Case | 16-CDIP |
| Supplier Device Package | 16-CDIP |
| Type | Priority Encoder |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
| Voltage Supply Source | Dual Supply |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 23.61 | |
| 100 | $ 20.63 | |||
| 250 | $ 15.90 | |||
| 1000 | $ 14.23 | |||
Description
General part information
CD4532B-MIL Series
CD4532B consists of combinational logic that encodes the highest priority input (D7-D0) to a 3-bit binary code. The eight inputs, D7 through D0, each have an assigned priority; D7 is the highest priority and D0 is the lowest. The priority encoder is inhibited when the chip-enable input EIis low. When EIis high, the binary representation of the highest-priority input appears on output lines Q2-Q0, and the group select line GS is high to indicate that priority inputs are present. The enable-out (EO) is high when no priority inputs are present. If any one input is high, EOis low and all cascaded lower-order stages are disabled.
The CD4532B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4532B consists of combinational logic that encodes the highest priority input (D7-D0) to a 3-bit binary code. The eight inputs, D7 through D0, each have an assigned priority; D7 is the highest priority and D0 is the lowest. The priority encoder is inhibited when the chip-enable input EIis low. When EIis high, the binary representation of the highest-priority input appears on output lines Q2-Q0, and the group select line GS is high to indicate that priority inputs are present. The enable-out (EO) is high when no priority inputs are present. If any one input is high, EOis low and all cascaded lower-order stages are disabled.
Documents
Technical documentation and resources