Catalog
CMOS 8-Bit Priority Encoder
Key Features
• Converts from 1 of 8 to binaryProvides cascading feature to handle any number of inputsGroup select indicates one or more priority inputsStandardized, symmetrical output characteristics100% tested for quiescent current at 20 VMaximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°CNoise margin (full package-temperature range):0.5 V at VDD= 5 V1.5 V at VDD= 10 V1.5 V at VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"Applications:Priority encoderBinary or BCD encoder (keyboard encoding)Floating point arithmeticData sheet acquired from Harris SemiconductorConverts from 1 of 8 to binaryProvides cascading feature to handle any number of inputsGroup select indicates one or more priority inputsStandardized, symmetrical output characteristics100% tested for quiescent current at 20 VMaximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°CNoise margin (full package-temperature range):0.5 V at VDD= 5 V1.5 V at VDD= 10 V1.5 V at VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"Applications:Priority encoderBinary or BCD encoder (keyboard encoding)Floating point arithmeticData sheet acquired from Harris Semiconductor
Description
AI
CD4532B consists of combinational logic that encodes the highest priority input (D7-D0) to a 3-bit binary code. The eight inputs, D7 through D0, each have an assigned priority; D7 is the highest priority and D0 is the lowest. The priority encoder is inhibited when the chip-enable input EIis low. When EIis high, the binary representation of the highest-priority input appears on output lines Q2-Q0, and the group select line GS is high to indicate that priority inputs are present. The enable-out (EO) is high when no priority inputs are present. If any one input is high, EOis low and all cascaded lower-order stages are disabled.
The CD4532B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
CD4532B consists of combinational logic that encodes the highest priority input (D7-D0) to a 3-bit binary code. The eight inputs, D7 through D0, each have an assigned priority; D7 is the highest priority and D0 is the lowest. The priority encoder is inhibited when the chip-enable input EIis low. When EIis high, the binary representation of the highest-priority input appears on output lines Q2-Q0, and the group select line GS is high to indicate that priority inputs are present. The enable-out (EO) is high when no priority inputs are present. If any one input is high, EOis low and all cascaded lower-order stages are disabled.
The CD4532B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).
