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DDA-8-SOIC Pkg
Integrated Circuits (ICs)

LP2998QMRX/NOPB

Active
Texas Instruments

DDR MEMORY TERMINATION REGULATOR 2.2V TO 5.5V 8-PIN HSOIC EP T/R AUTOMOTIVE AEC-Q100

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DDA-8-SOIC Pkg
Integrated Circuits (ICs)

LP2998QMRX/NOPB

Active
Texas Instruments

DDR MEMORY TERMINATION REGULATOR 2.2V TO 5.5V 8-PIN HSOIC EP T/R AUTOMOTIVE AEC-Q100

Technical Specifications

Parameters and characteristics for this part

SpecificationLP2998QMRX/NOPB
ApplicationsDDR, Converter
GradeAutomotive
Mounting TypeSurface Mount
Number of Outputs1
Operating Temperature [Max]125 ¯C
Operating Temperature [Min]-40 °C
Package / Case8-PowerSOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
QualificationAEC-Q100
Supplier Device Package8-SO PowerPad
Voltage - Input [Max]5.5 V
Voltage - Input [Min]2.2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.93
10$ 1.73
25$ 1.64
100$ 1.39
250$ 1.31
500$ 1.15
1000$ 0.95
Digi-Reel® 1$ 1.93
10$ 1.73
25$ 1.64
100$ 1.39
250$ 1.31
500$ 1.15
1000$ 0.95
Tape & Reel (TR) 2500$ 0.81
Texas InstrumentsLARGE T&R 1$ 1.45
100$ 1.20
250$ 0.86
1000$ 0.65

Description

General part information

LP2998-Q1 Series

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQmin of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREFoutput as a reference for the chipset and DIMMs.

An additional feature found on the LP2998 is an active low shutdown (SD) pin that provides Suspend To RAM (STR) functionality. WhenSDis pulled low the VTToutput will tri-state providing a high impedance output, but, VREFwill remain active. A power savings advantage can be obtained in this mode through lower quiescent current.

The LP2998 linear regulator is designed to meet JEDEC SSTL-2 and JEDEC SSTL-18 specifications for termination of DDR-SDRAM and DDR2 memory. The device also supports DDR3 and DDR3L VTT bus termination with VDDQmin of 1.35 V. The device contains a high-speed operational amplifier to provide excellent response to load transients. The output stage prevents shoot through while delivering 1.5 A continuous current and transient peaks up to 3 A in the application as required for DDR-SDRAM termination. The LP2998 also incorporates a VSENSE pin to provide superior load regulation and a VREFoutput as a reference for the chipset and DIMMs.