
AD5370BSTZ
Active40-CHANNEL, 16-BIT, SERIAL INPUT, VOLTAGE-OUTPUT DAC
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AD5370BSTZ
Active40-CHANNEL, 16-BIT, SERIAL INPUT, VOLTAGE-OUTPUT DAC
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Technical Specifications
Parameters and characteristics for this part
| Specification | AD5370BSTZ |
|---|---|
| Architecture | String DAC |
| Data Interface | DSP, SPI |
| Differential Output | False |
| INL/DNL (LSB) | ±4 (Max), ±1 (Max) |
| Mounting Type | Surface Mount |
| Number of Bits | 16 |
| Number of D/A Converters | 40 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Voltage - Buffered |
| Package / Case | 64-LQFP |
| Reference Type | External |
| Settling Time | 30 µs |
| Supplier Device Package | 64-LQFP (10x10) |
| Voltage - Supply, Analog [Max] | 16.5 V |
| Voltage - Supply, Analog [Min] | -4.5 V, 9 V |
| Voltage - Supply, Digital [Max] | 5.5 V |
| Voltage - Supply, Digital [Min] | 2.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 133.04 | |
| 10 | $ 108.77 | |||
| 25 | $ 103.94 | |||
Description
General part information
AD5370 Series
The AD5370* contains forty 16-bit DACs in a single 64-lead LFCSP and a 64-lead LQFP. The device provides buffered voltage outputs with a span that is 4× the reference voltage. The gain and offset of each DAC channel can be independently trimmed to remove errors. For even greater flexibility, the device is divided into five groups of eight DACs. Three offset DAC channels allow the output range of blocks to be adjusted. Group 0 can be adjusted by Offset DAC 0, Group 1 can be adjusted by Offset DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.The AD5370 offers guaranteed operation over a wide supply range, with VSS from −16.5 V to −4.5 V and VDD from +9 V to +16.5 V. The output amplifier headroom requirement is 1.4 V operating with a load current of 1 mA.The AD5370 has a high speed serial interface that is compatible with SPI, QSPI™, MICROWIRE™, and DSP interface standards and can handle clock speeds of up to 50 MHz.The DAC registers are updated on receipt of new data. All the outputs can be updated simultaneously by taking theLDACinput low. Each channel has a programmable gain and an offset adjust register to allow removal of gain and offset errors.Each DAC output is gained and buffered on chip with respect to an external SIGGNDx input. The DAC outputs can also be switched to SIGGNDx via theCLRpin.ApplicationsLevel setting in automatic test equipment (ATE)Variable optical attenuators (VOA)Optical switchesIndustrial control systemsInstrumentation* Protected by U.S. Patent No. 5,969,657; other patents pending.
Documents
Technical documentation and resources