The NB3N51044 is a precision, low phase noise clock generator that supports PCI Express and sRIO clock requirements. The device accepts a 25 MHz fundamental mode parallel resonant crystal or a 25 MHz single ended reference clock signal and generates four differential HCSL/LVDS outputs of 100 MHz or 125 MHz clock frequency based on frequency select input F_SEL. NB3N51044 is configurable to bypass the PLL from signal path using BYPASS, and provides the output frequency through the divider network. All clock outputs can be individually enabled / disabled through hardware input pins OE. In addition, device can be reset using Master Reset input pin MR_OE#.