
LTC2209IUP#PBF
ActiveANALOG TO DIGITAL CONVERTER, 16 BIT, 160 MSPS, DIFFERENTIAL, SINGLE ENDED, PARALLEL, SINGLE
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LTC2209IUP#PBF
ActiveANALOG TO DIGITAL CONVERTER, 16 BIT, 160 MSPS, DIFFERENTIAL, SINGLE ENDED, PARALLEL, SINGLE
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Technical Specifications
Parameters and characteristics for this part
| Specification | LTC2209IUP#PBF |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | Parallel, LVDS - Parallel |
| Features | PGA |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 1 |
| Number of Bits | 16 |
| Number of Inputs [custom] | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 C |
| Package / Case | 64-WFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | Internal, External |
| Sampling Rate (Per Second) | 160 M |
| Supplier Device Package | 64-QFN |
| Supplier Device Package [x] | 9 |
| Supplier Device Package [y] | 9 |
| Voltage - Supply, Analog [Max] | 3.465 V |
| Voltage - Supply, Analog [Min] | 3.135 V |
| Voltage - Supply, Digital [Max] | 3.465 V |
| Voltage - Supply, Digital [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
LTC2209 Series
The LTC2209 is a 160Msps 16-bit A/D converter designed for digitizing high frequency, wide dynamic range signals with input frequencies up to 700MHz. The input range of the ADC can be optimized with the PGA front end.The LTC2209 is perfect for demanding communications applications, with AC performance that includes 77.3dBFS Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low jitter of 70fsRMSallows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±5.5LSB INL, ±1LSB DNL (no missing codes).The digital output can be either differential LVDS or single-ended CMOS. There are two format options for the CMOS outputs: a single bus running at the full data rate or demultiplexed busses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.6V.The ENC+and ENC–inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.ApplicationsTelecommunicationsReceiversCellular Base StationsSpectrum AnalysisImaging Systems
Documents
Technical documentation and resources