Specification	SN74LS107ANSR

Clock Frequency	45 MHz
Current - Output High, Low [custom]	400 µA
Current - Output High, Low [custom]	8 mA
Current - Quiescent (Iq)	6 mA
Max Propagation Delay @ V, Max CL	20 ns
Mounting Type	Surface Mount
Number of Bits per Element	1
Number of Elements	2
Operating Temperature [Max]	70 °C
Operating Temperature [Min]	0 °C
Output Type	Complementary
Package / Case	14-SOIC
Package / Case [x]	0.209 "
Package / Case [y]	5.3 mm
Supplier Device Package	14-SO
Trigger Type	Negative Edge
Type	JK Type
Voltage - Supply [Max]	5.25 V
Voltage - Supply [Min]	4.75 V

SN74LS107A Series

Dual J-K Flip-Flops With Clear

Part	Current - Quiescent (Iq)	Number of Bits per Element	Function	Output Type	Mounting Type	Number of Elements	Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Clock Frequency	Trigger Type	Package / Case [x]	Package / Case [y]	Package / Case	Max Propagation Delay @ V, Max CL	Operating Temperature [Max]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package
Texas Instruments SN74LS107AD	6 mA	1	Reset	Complementary	Surface Mount	2	JK Type	4.75 V	5.25 V	45 MHz	Negative Edge	0.154 in	3.9 mm	14-SOIC	20 ns	70 °C	400 µA	8 mA
Texas Instruments SN74LS107ADR	6 mA	1		Complementary	Surface Mount	2	JK Type	4.75 V	5.25 V	45 MHz	Negative Edge	0.154 in	3.9 mm	14-SOIC	20 ns	70 °C	400 µA	8 mA
Texas Instruments SN74LS107ANSR	6 mA	1		Complementary	Surface Mount	2	JK Type	4.75 V	5.25 V	45 MHz	Negative Edge	0.209 "	5.3 mm	14-SOIC	20 ns	70 °C	400 µA	8 mA	14-SO
Texas Instruments SN74LS107AN	6 mA	1		Complementary	Through Hole	2	JK Type	4.75 V	5.25 V	45 MHz	Negative Edge	0.3 "	7.62 mm	14-DIP	20 ns	70 °C	400 µA	8 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	2000	$ 1.22
		6000	$ 1.18
Texas Instruments	LARGE T&R	1	$ 2.31
		100	$ 1.90
		250	$ 1.37
		1000	$ 1.03

Description

General part information

SN74LS107A Series

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.

The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.

Documents

Technical documentation and resources

Dual J-K Flip-Flops With Clear datasheet

Data sheet