SN74LS107A Series

Dual J-K Flip-Flops With Clear

Catalog

Dual J-K Flip-Flops With Clear

Part	Current - Quiescent (Iq)	Number of Bits per Element	Function	Output Type	Mounting Type	Number of Elements	Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Clock Frequency	Trigger Type	Package / Case [x]	Package / Case [y]	Package / Case	Max Propagation Delay @ V, Max CL	Operating Temperature [Max]	Current - Output High, Low [custom]	Current - Output High, Low [custom]	Supplier Device Package
Texas Instruments SN74LS107AD	6 mA	1	Reset	Complementary	Surface Mount	2	JK Type	4.75 V	5.25 V	45 MHz	Negative Edge	0.154 in	3.9 mm	14-SOIC	20 ns	70 °C	400 µA	8 mA
Texas Instruments SN74LS107ADR	6 mA	1		Complementary	Surface Mount	2	JK Type	4.75 V	5.25 V	45 MHz	Negative Edge	0.154 in	3.9 mm	14-SOIC	20 ns	70 °C	400 µA	8 mA
Texas Instruments SN74LS107ANSR	6 mA	1		Complementary	Surface Mount	2	JK Type	4.75 V	5.25 V	45 MHz	Negative Edge	0.209 "	5.3 mm	14-SOIC	20 ns	70 °C	400 µA	8 mA	14-SO
Texas Instruments SN74LS107AN	6 mA	1		Complementary	Through Hole	2	JK Type	4.75 V	5.25 V	45 MHz	Negative Edge	0.3 "	7.62 mm	14-DIP	20 ns	70 °C	400 µA	8 mA

Catalog

Dual J-K Flip-Flops With Clear

Key Features

• Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPsDependable Texas Instruments Quality and ReliabilityPackage Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Plastic and Ceramic DIPsDependable Texas Instruments Quality and Reliability

Description

The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high. The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high. The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C. The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high. The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high. The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.