This JEDEC SSTE32882-compliant, 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for operation on DDR3 registered DIMMs with VDDof 1.5 V and on DDR3L registered DIMMs with VDDof 1.35 V.

All inputs are 1.5 V and 1.35 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn andYnand control net outputs DxCKEn,DxCSnand DxODTn can be driven with a different strength and skew to optimize signal integrity, compensate for different loading and equalize signal travel speed.

The SN74SSQEA32882 has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When theQCSENinput pin is open (or pulled high), the component has two chip select inputs,DCS0andDCS1, and two copies of each chip select output,QACS0,QACS1,QBCS0andQBCS1. This is the "QuadCS disabled" mode. When theQCSENinput pin is pulled low, the component has four chip select inputsDCS[3:0], and four chip select outputs,QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of this specification,DCS[n:0]will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for QuadCS enabled.QxCS[n:0]will indicate all of the chip select outputs.Read more