Integrated Circuits (ICs)

SN74ALVCH374DW

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OCTAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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Search across all available documentation for this part.

DocumentsMigration From 3.3-V To 2.5-V Power Supplies For Logic Devices CMOS Power Consumption and CPD Calculation (Rev. B)+18

Integrated Circuits (ICs)

SN74ALVCH374DW

Active

Texas Instruments

OCTAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

Deep-Dive with AI

DocumentsMigration From 3.3-V To 2.5-V Power Supplies For Logic Devices CMOS Power Consumption and CPD Calculation (Rev. B)+18

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74ALVCH374DW

Clock Frequency	150 MHz
Current - Output High, Low	24 mA
Current - Quiescent (Iq)	10 µA
Function	Standard
Input Capacitance	5 pF
Max Propagation Delay @ V, Max CL	3.6 ns
Mounting Type	Surface Mount
Number of Bits per Element	8
Number of Elements	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Non-Inverted
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Trigger Type	Positive Edge
Type	D-Type
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	1.65 V

SN74ALVCH374 Series

Octal Positive-Edge-Triggered D-Type Flip-Flop With 3-State Outputs

Part	Function	Trigger Type	Type	Mounting Type	Voltage - Supply [Min]	Voltage - Supply [Max]	Number of Bits per Element	Current - Quiescent (Iq)	Package / Case	Package / Case [y]	Package / Case [y]	Input Capacitance	Output Type	Operating Temperature [Max]	Operating Temperature [Min]	Number of Elements	Clock Frequency	Max Propagation Delay @ V, Max CL	Supplier Device Package	Current - Output High, Low	Package / Case [x]	Package / Case	Package / Case
Texas Instruments SN74ALVCH374DW	Standard	Positive Edge	D-Type	Surface Mount	1.65 V	3.6 V	8	10 µA	20-SOIC	0.295 in	7.5 mm	5 pF	Non-Inverted Tri-State	85 °C	-40 °C	1	150 MHz	3.6 ns	20-SOIC	24 mA
Texas Instruments SN74ALVCH374DBR	Standard	Positive Edge	D-Type	Surface Mount	1.65 V	3.6 V	8	10 µA	20-SSOP			5 pF	Non-Inverted Tri-State	85 °C	-40 °C	1	150 MHz	3.6 ns	20-SSOP	24 mA
Texas Instruments SN74ALVCH374PWR	Standard	Positive Edge	D-Type	Surface Mount	1.65 V	3.6 V	8	10 µA	20-TSSOP	4.4 mm		5 pF	Non-Inverted Tri-State	85 °C	-40 °C	1	150 MHz	3.6 ns	20-TSSOP	24 mA	0.173 in
Texas Instruments SN74ALVCH374DWR	Standard	Positive Edge	D-Type	Surface Mount	1.65 V	3.6 V	8	10 µA	20-SOIC	0.295 in	7.5 mm	5 pF	Non-Inverted Tri-State	85 °C	-40 °C	1	150 MHz	3.6 ns	20-SOIC	24 mA
Texas Instruments SN74ALVCH374DGVR	Standard	Positive Edge	D-Type	Surface Mount	1.65 V	3.6 V	8	10 µA	20-TFSOP	0.173 in	4.4 mm	5 pF	Non-Inverted Tri-State	85 °C	-40 °C	1	150 MHz	3.6 ns	20-TVSOP	24 mA
Texas Instruments SN74ALVCH374DWRE4	Standard	Positive Edge	D-Type	Surface Mount	1.65 V	3.6 V	8	10 µA	20-SOIC	0.295 in	7.5 mm	5 pF	Non-Inverted Tri-State	85 °C	-40 °C	1	150 MHz	3.6 ns	20-SOIC	24 mA
Texas Instruments SN74ALVCH374PW	Standard	Positive Edge	D-Type	Surface Mount	1.65 V	3.6 V	8	10 µA	20-TSSOP	4.4 mm		5 pF	Non-Inverted Tri-State	85 °C	-40 °C	1	150 MHz	3.6 ns	20-TSSOP	24 mA	0.173 in
Texas Instruments SN74ALVCH374N	Standard	Positive Edge	D-Type	Through Hole	1.65 V	3.6 V	8	10 µA	20-DIP			5 pF	Non-Inverted Tri-State	85 °C	-40 °C	1	150 MHz	3.6 ns	20-PDIP	24 mA		7.62 mm	0.3 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 0.76
		10	$ 0.68
		25	$ 0.65
		100	$ 0.53
		250	$ 0.50
		500	$ 0.44
		1000	$ 0.41
Texas Instruments	TUBE	1	$ 0.62
		100	$ 0.47
		250	$ 0.35
		1000	$ 0.25

Description

General part information

SN74ALVCH374 Series

This octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCCoperation.

The SN74ALVCH374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

Documents

Technical documentation and resources

SN74ALVCH374DW

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SN74ALVCH374DW

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Technical Specifications

SN74ALVCH374 Series

Pricing

Description

SN74ALVCH374 Series

Documents

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

CMOS Power Consumption and CPD Calculation (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Live Insertion

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

ALVC Advanced Low-Voltage CMOS Including SSTL, HSTL, And ALB (Rev. B)

SN74ALVCH374 datasheet (Rev. G)

Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)

Input and Output Characteristics of Digital Integrated Circuits

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Logic Guide (Rev. AB)

LOGIC Pocket Data Book (Rev. B)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Understanding Advanced Bus-Interface Products Design Guide

Power-Up Behavior of Clocked Devices (Rev. B)

TI SN74ALVC16835 Component Specification Analysis for PC100

Standard Linear & Logic for PCs, Servers & Motherboards

Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

SN74ALVCH374 Series