Integrated Circuits (ICs)

DRA712BGGCBDQ1

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600 MHZ ARM CORTEX-A15 SOC PROCESSOR WITH GRAPHICS & DUAL ARM CORTEX-M4 FOR INFOTAINMENT & CLUSTER

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Search across all available documentation for this part.

DocumentsJacinto6 Spread Spectrum Clocking Configuration (Rev. A)Android Boot Optimization on DRA7xx Devices (Rev. A)+40

Integrated Circuits (ICs)

DRA712BGGCBDQ1

Active

Texas Instruments

600 MHZ ARM CORTEX-A15 SOC PROCESSOR WITH GRAPHICS & DUAL ARM CORTEX-M4 FOR INFOTAINMENT & CLUSTER

Deep-Dive with AI

DocumentsJacinto6 Spread Spectrum Clocking Configuration (Rev. A)Android Boot Optimization on DRA7xx Devices (Rev. A)+40

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	DRA712BGGCBDQ1

Additional Interfaces	USB, I2C, SPI, Ethernet, 1-Wire®, IrDA, McSPI, CANbus, McASP, MMC/SD/SDIO, UART/USART, DMA
Co-Processors/DSP	GPU, ARM® Cortex®-M4, BB2D, IVA
Core Processor	ARM® Cortex®-A15
Display & Interface Controllers	HDMI, LCD
Ethernet	1Gbps
Ethernet	10/100/1000Mbps
Grade	Automotive
Graphics Acceleration	True
Mounting Type	Surface Mount
Number of Cores/Bus Width	32 Bit, 1 Core
Operating Temperature [Max]	125 ¯C
Operating Temperature [Min]	-40 °C
Package / Case	FCBGA, 538-LFBGA
Qualification	AEC-Q100
RAM Controllers	DDR3L, DDR3
Security Features	Software IP Protection, Device Identity, Secure Boot, Secure Storage, Cryptography, Isolation Firewalls, Debug Security
Speed	400 MHz
Supplier Device Package	538-FCBGA (17x17)
USB	USB 2.0 (2), USB 3.0 (1)
Voltage - I/O	1.5 V, 1.35 V, 3.3 V, 1.8 V

DRA712 Series

600 MHz Arm Cortex-A15 SoC processor with graphics & dual Arm Cortex-M4 for infotainment & cluster

Part	Ethernet	Ethernet	Core Processor	Grade	Co-Processors/DSP	Qualification	Package / Case	Supplier Device Package	USB	RAM Controllers	Graphics Acceleration	Display & Interface Controllers	Voltage - I/O	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Speed	Security Features	Number of Cores/Bus Width	Additional Interfaces
Texas Instruments DRA712BGGCBDQ1	1Gbps	10/100/1000Mbps	ARM® Cortex®-A15	Automotive	ARM® Cortex®-M4 BB2D GPU IVA	AEC-Q100	538-LFBGA FCBGA	538-FCBGA (17x17)	USB 2.0 (2) USB 3.0 (1)	DDR3 DDR3L		HDMI LCD	1.35 V 1.5 V 1.8 V 3.3 V	-40 °C	125 ¯C	Surface Mount	400 MHz	Cryptography Debug Security Device Identity Isolation Firewalls Secure Boot Secure Storage Software IP Protection	1 Core 32 Bit	1-Wire® CANbus DMA Ethernet I2C IrDA McASP McSPI MMC/SD/SDIO SPI UART/USART USB

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

DRA712 Series

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package.

The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities.

Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Documents

Technical documentation and resources

DRA712BGGCBDQ1

Deep-Dive with AI

DRA712BGGCBDQ1

Deep-Dive with AI

Technical Specifications

DRA712 Series

Pricing

Description

DRA712 Series

Documents

Jacinto6 Spread Spectrum Clocking Configuration (Rev. A)

Android Boot Optimization on DRA7xx Devices (Rev. A)

Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B)

Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A)

Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices

Robust Rear-View Camera (RVC) App Report

Sharing VPE Between VISIONSDK and PSDKLA

Tools and Techniques to Root Case Failures in Video Capture Subsystem

IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC

The Implementation of YUV422 Output for SRV

DRA74x_75x/DRA72x Performance (Rev. A)

Gstreamer Migration Guidelines

Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A)

Optimization of GPU-Based Surround View on TI’s TDA2x SoC

DRA71x and DRA72x Technical Reference Manual (Rev. D)

DRA71x Cost Effective Automotive Reference Design

DRA71x EVM CPU board user's guide (Rev. B)

Achieving Early CAN Response on DRA7xx Devices

ECC/EDC on TDAxx (Rev. B)

DRA72x and DRA71x SoC for Automotive Infortainment Silicon Errata (Rev. F)

A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B)

Flashing Binaries to DRA7xx Factory Boards Using DFU

Jump Start Upgrading Your Digital Cluster Design with Jacinto 6 Platform (Rev. A)

Tools and Techniques for Audio Debugging

Debugging Tools and Techniques With IPC3.x

DRA71x Infotainment Applications Processor datasheet (Rev. G)

MMC DLL Tuning (Rev. B)

Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC

Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A)

Today’s high-end infotainment soon becoming mainstream

Informational ADAS as Software Upgrade to Today’s Infotainment Systems

Early Splash Screen on DRA7x Devices

Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices

Integrating New Cameras With Video Input Port on DRA7xx SoCs

AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E)

Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device

Jacinto6 Android Video Encoder Software Design Specification User's Guide

Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A)

Linux Boot Time Optimizations on DRA7xx Devices

Jacinto6 Android Video Decoder Software Design Specification User's Guide

Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices

Integrating AUTOSAR on TI SoC: Fundamentals

DRA712 Series