DRA712 Series

600 MHz Arm Cortex-A15 SoC processor with graphics & dual Arm Cortex-M4 for infotainment & cluster

Catalog

600 MHz Arm Cortex-A15 SoC processor with graphics & dual Arm Cortex-M4 for infotainment & cluster

Part	Ethernet	Ethernet	Core Processor	Grade	Co-Processors/DSP	Qualification	Package / Case	Supplier Device Package	USB	RAM Controllers	Graphics Acceleration	Display & Interface Controllers	Voltage - I/O	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Speed	Security Features	Number of Cores/Bus Width	Additional Interfaces
Texas Instruments DRA712BGGCBDQ1	1Gbps	10/100/1000Mbps	ARM® Cortex®-A15	Automotive	ARM® Cortex®-M4 BB2D GPU IVA	AEC-Q100	538-LFBGA FCBGA	538-FCBGA (17x17)	USB 2.0 (2) USB 3.0 (1)	DDR3 DDR3L		HDMI LCD	1.35 V 1.5 V 1.8 V 3.3 V	-40 °C	125 ¯C	Surface Mount	400 MHz	Cryptography Debug Security Device Identity Isolation Firewalls Secure Boot Secure Storage Software IP Protection	1 Core 32 Bit	1-Wire® CANbus DMA Ethernet I2C IrDA McASP McSPI MMC/SD/SDIO SPI UART/USART USB

Catalog

600 MHz Arm Cortex-A15 SoC processor with graphics & dual Arm Cortex-M4 for infotainment & cluster

Key Features

• Architecture designed for infotainment applicationsVideo, image, and graphics processing supportFull-HD video (1920 × 1080p, 60 fps)Multiple video input and video output2D and 3D graphicsArm®Cortex®-A15 microprocessor subsystemC66x floating-point VLIW DSPFully object-code compatible with C67x and C64x+Up to thirty-two 16 × 16-bit fixed-point multiplies per cycleUp to 512KB of on-chip L3 RAMLevel 3 (L3) and Level 4 (L4) interconnectsDDR3/DDR3L Memory Interface (EMIF) moduleSupports up to DDR-1333 (667 MHz)Up to 2GB across single chip selectDual Arm® Cortex®-M4 Image Processing Units (IPU)IVA-HD subsystemDisplay subsystemDisplay controller With DMA engine and up to three pipelinesHDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant2D-graphics accelerator (BB2D) subsystemVivante®GC320 coreVideo Processing Engine (VPE)Single-core PowerVR™ SGX544 3D GPUOne Video Input Port (VIP) moduleSupport for up to four multiplexed input portsGeneral-Purpose Memory Controller (GPMC)Enhanced Direct Memory Access (EDMA) controller2-port gigabit ethernet (GMAC)Up to two external portsSixteen 32-bit general-purpose timers32-Bit MPU watchdog timerSix high-speed inter-integrated circuit (I2C) portsHDQ™/1-Wire®interfaceTen configurable UART/IrDA/CIR modulesFour Multichannel Serial Peripheral Interfaces (McSPI)Quad SPI Interface (QSPI)Media Local Bus Subsystem (MLBSS)Eight Multichannel Audio Serial Port (McASP) modulesSuperSpeed USB 3.0 dual-role deviceHigh-speed USB 2.0 dual-role deviceHigh-speed USB 2.0 on-the-goFour MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)PCI Express®3.0 subsystems with two 5-Gbps lanesOne 2-lane Gen2-compliant portor two 1-lane Gen2-compliant portsDual Controller Area Network (DCAN) modulesCAN 2.0B protocolMIPI®CSI-2 camera serial interfaceUp to 186 General-Purpose I/O (GPIO) pinsDevice security featuresHardware crypto accelerators and DMAFirewallsJTAG lockSecure keysSecure ROM and bootCustomer programmable keysPower, reset, and clock managementOn-chip debug with CTools technology28-nm CMOS technology17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)Architecture designed for infotainment applicationsVideo, image, and graphics processing supportFull-HD video (1920 × 1080p, 60 fps)Multiple video input and video output2D and 3D graphicsArm®Cortex®-A15 microprocessor subsystemC66x floating-point VLIW DSPFully object-code compatible with C67x and C64x+Up to thirty-two 16 × 16-bit fixed-point multiplies per cycleUp to 512KB of on-chip L3 RAMLevel 3 (L3) and Level 4 (L4) interconnectsDDR3/DDR3L Memory Interface (EMIF) moduleSupports up to DDR-1333 (667 MHz)Up to 2GB across single chip selectDual Arm® Cortex®-M4 Image Processing Units (IPU)IVA-HD subsystemDisplay subsystemDisplay controller With DMA engine and up to three pipelinesHDMI™ encoder: HDMI 1.4a and DVI 1.0 compliant2D-graphics accelerator (BB2D) subsystemVivante®GC320 coreVideo Processing Engine (VPE)Single-core PowerVR™ SGX544 3D GPUOne Video Input Port (VIP) moduleSupport for up to four multiplexed input portsGeneral-Purpose Memory Controller (GPMC)Enhanced Direct Memory Access (EDMA) controller2-port gigabit ethernet (GMAC)Up to two external portsSixteen 32-bit general-purpose timers32-Bit MPU watchdog timerSix high-speed inter-integrated circuit (I2C) portsHDQ™/1-Wire®interfaceTen configurable UART/IrDA/CIR modulesFour Multichannel Serial Peripheral Interfaces (McSPI)Quad SPI Interface (QSPI)Media Local Bus Subsystem (MLBSS)Eight Multichannel Audio Serial Port (McASP) modulesSuperSpeed USB 3.0 dual-role deviceHigh-speed USB 2.0 dual-role deviceHigh-speed USB 2.0 on-the-goFour MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)PCI Express®3.0 subsystems with two 5-Gbps lanesOne 2-lane Gen2-compliant portor two 1-lane Gen2-compliant portsDual Controller Area Network (DCAN) modulesCAN 2.0B protocolMIPI®CSI-2 camera serial interfaceUp to 186 General-Purpose I/O (GPIO) pinsDevice security featuresHardware crypto accelerators and DMAFirewallsJTAG lockSecure keysSecure ROM and bootCustomer programmable keysPower, reset, and clock managementOn-chip debug with CTools technology28-nm CMOS technology17 mm × 17 mm, 0.65-mm pitch, 538-pin BGA (CBD)

Description

The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package. The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities. Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard. The device features a simplified power supply rail mapping which enables lower cost PMIC solutions. The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package. The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities. Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard. The device features are simplified power supply rail mapping which enables lower cost PMIC solutions. The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package. The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities. Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Arm Neon™ extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard. The device features a simplified power supply rail mapping which enables lower cost PMIC solutions. The DRA71x processor is offered in a 538-ball, 17×17-mm, 0.65-mm ball pitch (0.8mm spacing rules can be used on signals) with Via Channel™ Array (VCA) technology, ball grid array (BGA) package. The architecture is designed to deliver high-performance concurrencies for automotive applications in a cost-effective solution, providing full scalability from the DRA75x ("Jacinto 6 EP" and "Jacinto 6 Ex"), DRA74x "Jacinto 6" and DRA72x "Jacinto 6 Eco" family of infotainment processors, including graphics, voice, HMI, multimedia and smartphone projection mode capabilities. Programmability is provided by a single-core Arm Cortex-A15 RISC CPU with Neon extensions and a TI C66x VLIW floating-point DSP core. The Arm processor lets developers keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. Additionally, TI provides a complete set of development tools for the Arm, and DSP, including C compilers and a debugging interface for visibility into source code execution. Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative. The DRA71x Jacinto 6 Entry processor family is qualified according to the AEC-Q100 standard. The device features are simplified power supply rail mapping which enables lower cost PMIC solutions.