CD74HC597E
ActiveSHIFT REGISTER SINGLE 8-BIT SERIAL/PARALLEL TO SERIAL 16-PIN PDIP TUBE
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CD74HC597E
ActiveSHIFT REGISTER SINGLE 8-BIT SERIAL/PARALLEL TO SERIAL 16-PIN PDIP TUBE
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC597E |
|---|---|
| Function | Parallel or Serial to Serial |
| Logic Type | Shift Register |
| Mounting Type | Through Hole |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Push-Pull |
| Package / Case | 0.3 in |
| Package / Case | 16-DIP |
| Package / Case | 7.62 mm |
| Supplier Device Package | 16-PDIP |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 1 | $ 0.42 | |
| 10 | $ 0.33 | |||
| 25 | $ 0.33 | |||
| 100 | $ 0.29 | |||
| 250 | $ 0.29 | |||
| 500 | $ 0.28 | |||
| Digikey | Tube | 1 | $ 0.78 | |
| 10 | $ 0.69 | |||
| 25 | $ 0.64 | |||
| 100 | $ 0.53 | |||
| 250 | $ 0.49 | |||
| 500 | $ 0.42 | |||
| 1000 | $ 0.33 | |||
| 2500 | $ 0.30 | |||
| 5000 | $ 0.28 | |||
| Texas Instruments | TUBE | 1 | $ 0.66 | |
| 100 | $ 0.45 | |||
| 250 | $ 0.34 | |||
| 1000 | $ 0.23 | |||
Description
General part information
CD74HC597 Series
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.
Documents
Technical documentation and resources
