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SPC56EC74B3C9EEX
Integrated Circuits (ICs)

SPC56EC74B3C9EEX

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STMicroelectronics

32-BIT POWER ARCHITECTURE MCU FOR AUTOMOTIVE BODY AND GATEWAY APPLICATIONS

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SPC56EC74B3C9EEX
Integrated Circuits (ICs)

SPC56EC74B3C9EEX

Active
STMicroelectronics

32-BIT POWER ARCHITECTURE MCU FOR AUTOMOTIVE BODY AND GATEWAY APPLICATIONS

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSPC56EC74B3C9EEX
ConnectivityUART/USART, CANbus, SPI, Ethernet, LINbus
Core Processore200z4d, e200z0h
Core Size32 Bit
Core SizeDual-Core
Data ConvertersA/D 33x10b, 10x12b
EEPROM Size64 K
GradeAutomotive
Mounting TypeSurface Mount
Number of I/O199
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Oscillator TypeInternal
Package / Case256-LBGA
PeripheralsDMA, PWM, POR, WDT
Program Memory Size1.5 MB
Program Memory TypeFLASH
QualificationAEC-Q100
RAM Size192 K
Speed120 MHz, 80 MHz
Supplier Device Package256-LBGA (17x17)
Voltage - Supply (Vcc/Vdd) [Max]5.5 V
Voltage - Supply (Vcc/Vdd) [Min]3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyN/A 0$ 16.01

Description

General part information

SPC56EC74B3 Series

The SPC564Bxx and SPC56ECxx is a new family of next generation microcontrollers built on the Power Architecture embedded category. This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device.

The SPC564Bxx and SPC56ECxx family expands the range of the SPC560B microcontroller family. It provides the scalability needed to implement platform approaches and delivers the performance required by increasingly sophisticated software architectures. The advanced and cost-efficient host processor core of the SPC564Bxx and SPC56ECxx automotive controller family complies with the Power Architecture embedded category, which is 100 percent user-mode compatible with the original Power Architecture user instruction set architecture (UISA). It operates at speeds of up to 120 MHz and offers high performance processing optimized for low power consumption. It also capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations.