Zenode.ai Logo
Beta
STMICROELECTRONICS M95128-DRMN3TP/K
Integrated Circuits (ICs)

570BILFT

Active
Renesas Electronics Corporation

ZERO DELAY BUFFER/MULTIPLIER, 85DEG C ROHS COMPLIANT: YES

Deep-Dive with AI

Search across all available documentation for this part.

STMICROELECTRONICS M95128-DRMN3TP/K
Integrated Circuits (ICs)

570BILFT

Active
Renesas Electronics Corporation

ZERO DELAY BUFFER/MULTIPLIER, 85DEG C ROHS COMPLIANT: YES

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

Specification570BILFT
Differential - Input:Output [custom]False
Differential - Input:Output [custom]False
Frequency - Max [Max]170 MHz
InputClock
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 C
OutputCMOS
Package / Case0.154 in
Package / Case8-SOIC
Package / Case3.9 mm
PLLTrue
Ratio - Input:Output1:2
Supplier Device Package8-SOIC
TypeZero Delay Buffer, Fanout Distribution, Spread Spectrum Clock Generator
Voltage - Supply [Max]3.45 V
Voltage - Supply [Min]3.15 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 3.83
10$ 3.44
25$ 3.25
100$ 2.82
250$ 2.67
500$ 2.40
1000$ 2.02
Digi-Reel® 1$ 3.83
10$ 3.44
25$ 3.25
100$ 2.82
250$ 2.67
500$ 2.40
1000$ 2.02
N/A 30$ 3.62
Tape & Reel (TR) 3000$ 1.92
MouserN/A 1$ 5.08
10$ 3.43
25$ 3.20
100$ 2.81
250$ 2.67
500$ 2.39
1000$ 2.02
3000$ 1.92
6000$ 1.85
NewarkEach (Supplied on Cut Tape) 1$ 3.76
10$ 2.84
25$ 2.61
50$ 2.48
100$ 2.35
250$ 2.23
500$ 2.15
1000$ 2.09

Description

General part information

570 Series

The IDT570 is a high-performance Zero Delay Buffer (ZDB) which integrates IDT's proprietary analog/digital Phase Locked Loop (PLL) techniques. The A version is recommended for 5 V designs and the B version for 3.3 V designs. The chip is part of IDT's ClockBlocks™ family, and was designed as a performance upgrade to meet today's higher speed and lower voltage requirements. The zero delay feature means that the rising edge of the input clock aligns with the rising edges of both output clocks, giving the appearance of no delay through the device. There are two outputs on the chip, one being a low-skew divide by two of the other output. The device incorporates an all-chip power down/tri-state mode that stops the internal PLL and puts both outputs into a high impedance state. The IDT570 is ideal for synchronizing outputs in a large variety of systems, from personal computers to data communications to graphIDT/video. By allowing off-chip feedback paths, the device can eliminate the delay through other devices.

Documents

Technical documentation and resources