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Technical Specifications
Parameters and characteristics for this part
| Specification | CD4029BPWG4 |
|---|---|
| Count Rate | 11 MHz |
| Direction | Up, Down |
| Logic Type | Binary Counter, Decade |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 4 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 16-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Reset | Asynchronous |
| Supplier Device Package | 16-TSSOP |
| Timing | Synchronous |
| Trigger Type | Positive Edge |
| Voltage - Supply [Max] | 18 V |
| Voltage - Supply [Min] | 3 V |
CD4029B Series
CMOS Presettable Up/Down Counter
| Part | Logic Type | Timing | Number of Elements | Direction | Reset | Supplier Device Package | Voltage - Supply [Max] | Voltage - Supply [Min] | Mounting Type | Number of Bits per Element | Count Rate | Trigger Type | Operating Temperature [Min] | Operating Temperature [Max] | Package / Case [x] | Package / Case | Package / Case [y] | Package / Case | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments | Binary Counter Decade | Synchronous | 1 | Down Up | Asynchronous | 16-TSSOP | 18 V | 3 V | Surface Mount | 4 | 11 MHz | Positive Edge | -55 °C | 125 °C | 0.173 in | 16-TSSOP | 4.4 mm | ||
 Texas Instruments | Binary Counter Decade | Synchronous | 1 | Down Up | Asynchronous | 16-SOIC | 18 V | 3 V | Surface Mount | 4 | 11 MHz | Positive Edge | -55 °C | 125 °C | 0.154 in | 16-SOIC | 3.9 mm | ||
 Texas Instruments | Binary Counter Decade | Synchronous | 1 | Down Up | Asynchronous | 16-PDIP | 18 V | 3 V | Through Hole | 4 | 11 MHz | Positive Edge | -55 °C | 125 °C | 16-DIP | 0.3 in | 7.62 mm | ||
 Texas Instruments | Binary Counter Decade | Synchronous | 1 | Down Up | Asynchronous | 16-TSSOP | 18 V | 3 V | Surface Mount | 4 | 11 MHz | Positive Edge | -55 °C | 125 °C | 0.173 in | 16-TSSOP | 4.4 mm | ||
Texas Instruments | Binary Counter Decade | Synchronous | 1 | Down Up | Asynchronous | 16-SOIC | 18 V | 3 V | Surface Mount | 4 | 11 MHz | Positive Edge | -55 °C | 125 °C | 0.154 in | 16-SOIC | 3.9 mm |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
CD4029B Series
CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs.
A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high. The CARRY-OUT\ signal is normally high and goes low when the counter reaches its maximum count in the UP mode or the minimum count in the DOWN mode provided the CARRY-IN\ signal is low. The CARRY-IN\ signal in the low state can thus be considered a CLOCK ENABLE\. The CARRY-IN\ terminal must be connected to VSSwhen not in use.
Binary counting is accomplished when the BINARY/DECADE input is high; the counter counts in the decade mode when the BINARY/DECADE input is low. The counter counts up when the UP/DOWN input is high, and down when the UP/DOWN input is low. Multiple packages can be connected in either a parallel-clocking or a ripple-clocking arrangement as shown in Fig. 17.
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