
AT32UC3B0512AU-Z2UR
ObsoleteIC MCU 32BIT 512KB FLASH 64QFN
Deep-Dive with AI
Search across all available documentation for this part.

AT32UC3B0512AU-Z2UR
ObsoleteIC MCU 32BIT 512KB FLASH 64QFN
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | AT32UC3B0512AU-Z2UR |
|---|---|
| Connectivity | USB, IrDA, I2C, SSC, UART/USART, SPI |
| Core Processor | AVR |
| Core Size | 32-Bit Single-Core |
| Data Converters [custom] | 8 |
| Data Converters [custom] | 10 |
| Mounting Type | Surface Mount |
| Number of I/O | 44 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 64-VFQFN Exposed Pad |
| Peripherals | Brown-out Detect/Reset, DMA, POR, WDT, PWM |
| Program Memory Size | 512 KB |
| Program Memory Type | FLASH |
| RAM Size | 96 K |
| Speed | 60 MHz |
| Supplier Device Package | 64-QFN (9x9) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
AT32UC3C1512C-AUTOMOTIVE Series
A complete system-on-chip 32-bit AVR microcontroller. It is designed for cost-sensitive embedded applications that require low power consumption, high code density and high performance.
The microprocessor's Memory Protection Unit (MPU) and fast, flexible interrupt controller support the latest real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions. The device incorporates on-chip flash and SRAM memories for secure and fast access. 64 KBytes of SRAM are directly coupled to the 32-bit AVR UC3 for performance optimization. Two blocks of 32 Kbytes SRAM are independently attached to the high speed bus matrix for real ping-pong management.
The microcontroller achieves exceptionally high data throughput by combining the multi-layered 32-bit AVR databus,128 KB on-chip SRAM with triple high speed interfaces, multi-channel peripheral, memory-to-memory DMA controller, high-speed USB embedded host, SD/SDIO card, MLC NAND flash with ECC, and SDRAM interfaces.
Documents
Technical documentation and resources