Zenode.ai Logo
Beta
28-SOIC Pkg
Integrated Circuits (ICs)

DAC811JU/1K

Obsolete
Texas Instruments

IC DAC 12BIT V-OUT 28SOIC

Deep-Dive with AI

Search across all available documentation for this part.

28-SOIC Pkg
Integrated Circuits (ICs)

DAC811JU/1K

Obsolete
Texas Instruments

IC DAC 12BIT V-OUT 28SOIC

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationDAC811JU/1K
ArchitectureR-2R
Data InterfaceParallel
Differential OutputFalse
INL/DNL (LSB)0.5 LSB, 0.25 LSB
Mounting TypeSurface Mount
Number of Bits12 bits
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Output TypeVoltage - Buffered
Package / Case28-SOIC
Package / Case [x]0.295 in
Package / Case [y]7.5 mm
Reference TypeInternal
Settling Time4 µs
Supplier Device Package28-SOIC
Voltage - Supply, Analog [Max]16.5 V
Voltage - Supply, Analog [Min]-11.4 V
Voltage - Supply, Digital5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

Description

General part information

DAC811 Series

The DAC811 is a complete, single-chip integrated-circuit, microprocessor-compatible, 12-bit digital-to-analog converter. The chip combines a precision voltage reference, microcomputer interface logic, and double-buffered latch, in a 12-bit D/A converter with a voltage output amplifier. Fast current switches and a laser-trimmed thin-film resistor network provide a highly accurate and fast D/A converter.

Microcomputer interfacing is facilitated by a double-buffered latch. The input latch is divided into three 4-bit nibbles to permit interfacing to 4-, 8-, 12-, or 16-bit buses and to handle right-or left-justified data. The 12-bit data in the input latches is transferred to the D/A latch to hold the output value.

Input gating logic is designed so that loading the last nibble or byte of data can be accomplished simultaneously with the transfer of data (previously stored in adjacent latches) from adjacent input latches to the D/A latch. This feature avoids spurious analog output values while using an interface technique that saves computer instructions.

Documents

Technical documentation and resources

No documents available