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44 QFP
Integrated Circuits (ICs)

AD7864ASZ-3REEL

Obsolete
Analog Devices

IC ADC 12BIT SAR 44MQFP

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44 QFP
Integrated Circuits (ICs)

AD7864ASZ-3REEL

Obsolete
Analog Devices

IC ADC 12BIT SAR 44MQFP

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationAD7864ASZ-3REEL
ArchitectureSAR
ConfigurationS/H-MUX-ADC
Data InterfaceParallel
FeaturesSimultaneous Sampling
Input TypeSingle Ended
Mounting TypeSurface Mount
Number of A/D Converters1
Number of Bits12 bits
Number of Inputs4
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case44-QFP
Ratio - S/H:ADC4:1
Reference TypeExternal, Internal
Sampling Rate (Per Second)520
Voltage - Supply, Analog5 V
Voltage - Supply, Digital5 V

Pricing

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Description

General part information

AD7864 Series

The AD7864 is a high speed, low power, 4-channel, simulta-neous sampling 12-bit analog-to-digital converter (ADC) that operates from a single 5 V supply. The part contains a 1.65 μs successive approximation ADC, four track-and-hold amplifiers, a 2.5 V reference, an on-chip clock oscillator, signal conditioning circuitry, and a high speed parallel interface. The input signals on four channels sample simultaneously preserving the relative phase information of the signals on the four analog inputs. The part accepts analog input ranges of ±10 V, ±5 V (AD7864-1), 0 V to +2.5 V, 0 V to +5 V (AD7864-2), and ±2.5 V (AD7864-3).Any subset of the four channels can be converted to maximize the throughput rate on the selected sequence. Select the channels to convert via hardware (channel select input pins) or software (programming the channel select register).A single conversion start signal(CONVST)simultaneously places all the track-and-holds into hold and initiates a conversion sequence for the selected channels. TheEOCsignal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence.Data is read from the part by a 12-bit parallel data bus using the standardCSandRDsignals. Maximum throughput for a single channel is 500 kSPS. For all four channels, the maximum throughput is 130 kSPS for the read-during-conversion sequence operation. The throughput rate for the read-after-conversion sequence operation depends on the read cycle time of the processor. See the Timing and Control section. The AD7864 is available in a small (0.3 square inch area) 44-lead MQFP.

Documents

Technical documentation and resources