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STMicroelectronics-ADC120IPT Analog to Digital Converters - ADCs 8-Channel Single ADC SAR 1Msps 12-bit Serial 16-Pin TSSOP T/R
Integrated Circuits (ICs)

M74HC4094YTTR

Active
STMicroelectronics

SHIFT REGISTER/LATCH SINGLE 8-BIT SERIAL TO SERIAL/PARALLEL AUTOMOTIVE AEC-Q100 16-PIN TSSOP T/R

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Search across all available documentation for this part.

DocumentsDS0301+1
STMicroelectronics-ADC120IPT Analog to Digital Converters - ADCs 8-Channel Single ADC SAR 1Msps 12-bit Serial 16-Pin TSSOP T/R
Integrated Circuits (ICs)

M74HC4094YTTR

Active
STMicroelectronics

SHIFT REGISTER/LATCH SINGLE 8-BIT SERIAL TO SERIAL/PARALLEL AUTOMOTIVE AEC-Q100 16-PIN TSSOP T/R

Deep-Dive with AI

DocumentsDS0301+1

Technical Specifications

Parameters and characteristics for this part

SpecificationM74HC4094YTTR
FunctionSerial to Parallel
GradeAutomotive
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element [custom]8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 C
Output TypeTri-State
Package / Case16-TSSOP
Package / Case [y]4.4 mm
Package / Case [y]0.173 in
QualificationAEC-Q100
Supplier Device Package16-TSSOP
Voltage - Supply [Max]6 V
Voltage - Supply [Min]2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 2500$ 0.64
5000$ 0.55
10000$ 0.50
DigikeyN/A 0$ 0.81
NewarkEach (Supplied on Cut Tape) 1$ 0.92
10$ 0.66
25$ 0.59
50$ 0.56
100$ 0.52
250$ 0.49
500$ 0.40
1000$ 0.37

Description

General part information

M74HC4094 Series

The M74HC4094 device is a high speed CMOS 8-bit SIPO shift latch register fabricated with silicon gate C2MOS technology. It consists of an 8-bit shift register and an 8-bit latch with 3-state output buffer. Data is shifted serially through the shift register on the positive going transition of the clock input signal. The output of the last stage (QS) can be used to cascade several devices.

Data on the QS output is transferred to a second output (QS’) on the following negative transition of the clock input signal. The data of each stage of the shift register is provided with a latch, which latches data on the negative going transition of the STROBE input signal. When the STROBE input is held high, data propagates through the latch to a 3-state output buffer. This buffer is enabled when OUTPUT ENABLE input is taken high. All inputs are equipped with protection circuits against static discharge and transient excess voltage.