STM32L021F4U6TR
ActiveARM MICROCONTROLLERS - MCU ULTRA-LOW-POWER ARM CORTEX-M0+ MCU 16-KBYTES OF FLASH , 32 MHZ CPU, AES
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STM32L021F4U6TR
ActiveARM MICROCONTROLLERS - MCU ULTRA-LOW-POWER ARM CORTEX-M0+ MCU 16-KBYTES OF FLASH , 32 MHZ CPU, AES
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Technical Specifications
Parameters and characteristics for this part
| Specification | STM32L021F4U6TR |
|---|---|
| Connectivity | IrDA, SPI, UART/USART, I2C |
| Core Processor | ARM® Cortex®-M0+ |
| Core Size | 32-Bit |
| Data Converters | A/D 7x12b |
| EEPROM Size [custom] | 512 |
| EEPROM Size [custom] | 8 |
| Mounting Type | Surface Mount |
| Number of I/O | 16 |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Oscillator Type | Internal |
| Package / Case | 20-UFQFN |
| Peripherals | Brown-out Detect/Reset, WDT, DMA, PWM, POR |
| Program Memory Size | 16 KB |
| Program Memory Type | FLASH |
| RAM Size | 2 K |
| Speed | 32 MHz |
| Supplier Device Package | 20-UFQFPN (3x3) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
STM32L021F4 Series
The access line ultra-low-power STM32L021x4 family incorporates the high-performance ARM® Cortex®-M0+ 32-bit RISC core operating at a 32 MHz frequency, high-speed embedded memories (16 Kbytes of Flash program memory, 512 bytes of data EEPROM and 2 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.
The STM32L021x4 devices provide high power efficiency for a wide range of performance. It is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes.
The STM32L021x4 devices offer several analog features, one 12-bit ADC with hardware oversampling, two ultra-low-power comparators, AES, several timers, one low-power timer (LPTIM), three general-purpose 16-bit timers, one RTC and one SysTick which can be used as timebases. They also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock.
Documents
Technical documentation and resources