STM32WB35CEU6A
ActiveULTRA-LOW-POWER DUAL CORE ARM CORTEX-M4 MCU 64 MHZ, CORTEX-M0+ 32 MHZ WITH 512 KBYTES OF FLASH MEMORY, BLUETOOTH LE 5.4, 802.15.4, ZIGBEE, THREAD, MATTER, USB, AES-256
STM32WB35CEU6A
ActiveULTRA-LOW-POWER DUAL CORE ARM CORTEX-M4 MCU 64 MHZ, CORTEX-M0+ 32 MHZ WITH 512 KBYTES OF FLASH MEMORY, BLUETOOTH LE 5.4, 802.15.4, ZIGBEE, THREAD, MATTER, USB, AES-256
Technical Specifications
Parameters and characteristics for this part
| Specification | STM32WB35CEU6A |
|---|---|
| Current - Receiving [Max] | 7.9 mA |
| Current - Receiving [Min] | 4.5 mA |
| Current - Transmitting [Max] | 12.7 mA |
| Current - Transmitting [Min] | 5.2 mA |
| Data Rate (Max) [Max] | 2 Mbps |
| Frequency | 2.4 GHz |
| GPIO | 30 |
| Memory Size | 96 kB, 512 kB |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 48-UFQFN Exposed Pad |
| Power - Output | 6 dBm |
| Protocol | Bluetooth v5.3, Zigbee® |
| RF Family/Standard | 802.15.4, Bluetooth |
| Sensitivity | -100 dBm |
| Serial Interfaces | I2S, UART, GPIO, IrDA, PWM, SPI, USART, ADC, JTAG, I2C |
| Supplier Device Package | 48-UFQFPN (7x7) |
| Type | TxRx + MCU |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.71 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
STM32WB35CE Series
The STM32WB55xx and STM32WB35xx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth®Low Energy SIG specification 5.4 and with IEEE 802.15.4-2011. They contain a dedicated Arm®Cortex®-M0+ for performing all the real-time low layer operation.
The devices are designed to be extremely low-power and are based on the high-performance Arm®Cortex®-M4 32-bit RISC core operating at a frequency of up to 64 MHz. This core features a Floating point unit (FPU) single precision that supports all Arm®single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.
Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.
Documents
Technical documentation and resources