STM32WL55JCI7
ActiveSUB-GHZ WIRELESS MICROCONTROLLERS. DUAL-CORE ARM CORTEX-M4/M0+ @48 MHZ WITH 256 KBYTES OF FLASH MEMORY, 64 KBYTES OF SRAM. LORA, (G)FSK, (G)MSK, BPSK MODULATIONS. AES 256-BIT. MULTIPROTOCOL SYSTEM-ON-CHIP.
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STM32WL55JCI7
ActiveSUB-GHZ WIRELESS MICROCONTROLLERS. DUAL-CORE ARM CORTEX-M4/M0+ @48 MHZ WITH 256 KBYTES OF FLASH MEMORY, 64 KBYTES OF SRAM. LORA, (G)FSK, (G)MSK, BPSK MODULATIONS. AES 256-BIT. MULTIPROTOCOL SYSTEM-ON-CHIP.
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Technical Specifications
Parameters and characteristics for this part
| Specification | STM32WL55JCI7 |
|---|---|
| Current - Receiving | 4.82 mA |
| Current - Transmitting [Max] | 120 mA |
| Current - Transmitting [Min] | 21 mA |
| Data Rate (Max) | 300 kbps |
| Frequency [Max] | 960 MHz |
| Frequency [Min] | 150 MHz |
| GPIO | 43 |
| Memory Size | 64 kB, 256 kB |
| Modulation | GMSK, GFSK, MSK, FSK, BPSK |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 73-UFBGA |
| Power - Output | 22 dBm |
| Protocol | LoRaWAN 1.0, Sigfox, LoRa |
| RF Family/Standard | General ISM < 1GHz |
| Sensitivity | -148 dBm |
| Serial Interfaces | I2S, UART, GPIO, IrDA, PWM, SPI, USART, ADC, JTAG, I2C |
| Supplier Device Package | 73-UFBGA (5x5) |
| Type | TxRx + MCU |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | N/A | 306 | $ 11.00 | |
Description
General part information
STM32WL55JC Series
The STM32WL55/54xx long-range wireless and ultra-low-power devices embed a powerful and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations: LoRa®, (G)FSK, (G)MSK, and BPSK.
The LoRa®modulation is available in STM32WLx5xx only.
These devices are designed to be extremely low-power and are based on the high-performance Arm®Cortex®-M4 32-bit RISC core operating at a frequency of up to 48 MHz. This core implements a full set of DSP instructions. It is complemented by an Arm®Cortex®-M0+ microcontroller. Both cores implement an independent memory protection unit (MPU) that enhances the application security.
Documents
Technical documentation and resources