STM32L552RCT6
ActiveULTRA-LOW-POWER WITH FPU ARM CORTEX-M33 WITH TRUST ZONE, MCU 110 MHZ WITH 256 KBYTES OF FLASH MEMORY
STM32L552RCT6
ActiveULTRA-LOW-POWER WITH FPU ARM CORTEX-M33 WITH TRUST ZONE, MCU 110 MHZ WITH 256 KBYTES OF FLASH MEMORY
Technical Specifications
Parameters and characteristics for this part
| Specification | STM32L552RCT6 |
|---|---|
| Connectivity | QSPI, SPI, UART/USART, USB, I2C, LINbus, IrDA, SAI, CANbus, MMC/SD |
| Core Processor | ARM® Cortex®-M33 |
| Core Size | 32-Bit |
| Data Converters | D/A 2x12b, A/D 16x12b |
| Mounting Type | Surface Mount |
| Number of I/O | 52 |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Oscillator Type | Internal |
| Package / Case | 64-LQFP |
| Peripherals | DMA, PWM, Brown-out Detect/Reset, WDT |
| Program Memory Size | 256 KB |
| Program Memory Type | FLASH |
| RAM Size | 256 K |
| Speed | 110 MHz |
| Supplier Device Package | 64-LQFP (10x10) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.71 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
STM32L552RC Series
The STM32L552xx devices are an ultra-low-power microcontrollers family (STM32L5 Series) based on the high-performance Arm®Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 110 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports all the Arm®single-precision data-processing instructions and all the data types. The Cortex®-M33 core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (512 Kbytes of Flash memory and 256 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), an Octo-SPI Flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources