The SNx4AHC74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. The SNx4AHC74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. For the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The ’AHCT125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. For the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design. These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.

The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer and microprocessor systems. During power-on,RESETis asserted when VDDreaches 1 V. After minimum VDD(≥ 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor: td= 2.1 × 104× CT Where CTis in faradstdis in seconds Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed sense threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time, td, has expired. In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor, the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.) The TLC77xxI is characterized for operation over a temperature range of –40°C to 85°C; the TLC77xxQ is characterized for operation over a temperature range of –40°C to 125°C; and the TLC77xxM is characterized for operation over the full Military temperature range of –55°C to 125°C. The 3×3 mm DRB package is also available as a non-magnetic package for medical imaging application. The TLC77xx family of micropower supply voltage supervisors provide reset control, primarily in microcomputer and microprocessor systems. During power-on,RESETis asserted when VDDreaches 1 V. After minimum VDD(≥ 2 V) is established, the circuit monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI(SENSE)) remains below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper system reset. The delay time, td, is determined by an external capacitor: td= 2.1 × 104× CT Where CTis in faradstdis in seconds Except for the TLC7701, which can be customized with two external resistors, each supervisor has a fixed sense threshold voltage set by an internal voltage divider. When SENSE voltage drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns above threshold voltage and the delay time, td, has expired. In addition to the power-on-reset and undervoltage-supervisor function, the TLC77xx adds power-down control support for static RAM. When CONTROL is tied to GND, RESET will act as active high. The voltage monitor contains additional logic intended for control of static memories with battery backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the TLC77xx and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor, the memory circuit is automatically disabled during a power loss. (In this application the TLC77xx power has to be supplied by the battery.) The TLC77xxI is characterized for operation over a temperature range of –40°C to 85°C; the TLC77xxQ is characterized for operation over a temperature range of –40°C to 125°C; and the TLC77xxM is characterized for operation over the full Military temperature range of –55°C to 125°C. The 3×3 mm DRB package is also available as a non-magnetic package for medical imaging application.

These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS244C. The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C. These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs. The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS244C. The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C.

These devices contain four independent 2-input NAND gates. They perform the Boolean functionsor Y = A\ + B\ in positive logic. The SN54F00 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F00 is characterized for operation from 0°C to 70°C. These devices contain four independent 2-input NAND gates. They perform the Boolean functionsor Y = A\ + B\ in positive logic. The SN54F00 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F00 is characterized for operation from 0°C to 70°C.

These devices contain three independent 3-input NAND gates. They perform the Boolean functionsorin positive logic. The SN54F10 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F10 is characterized for operation from 0°C to 70°C. These devices contain three independent 3-input NAND gates. They perform the Boolean functionsorin positive logic. The SN54F10 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F10 is characterized for operation from 0°C to 70°C.

These devices contain three independent 3-input AND gates. They perform the Boolean functionsorin positive logic. The SN54F11 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F11 is characterized for operation from 0°C to 70°C. These devices contain three independent 3-input AND gates. They perform the Boolean functionsorin positive logic. The SN54F11 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F11 is characterized for operation from 0°C to 70°C.

These data selectors/multiplexers contain inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections. The SN54F153 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F153 is characterized for operation from 0°C to 70°C. These data selectors/multiplexers contain inverters and drivers to supply full binary decoding data selection to the AND-OR gates. Separate strobe (G\) inputs are provided for each of the two 4-line sections. The SN54F153 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F153 is characterized for operation from 0°C to 70°C.