These devices contain six independent hex inverters with open-collector outputs. They perform the Boolean function Y = A\. The open-collector outputs require pullup resistors to perform correctly. These outputs can be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOHlevels. The SN54ALS05A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS05A is characterized for operation from 0°C to 70°C. These devices contain six independent hex inverters with open-collector outputs. They perform the Boolean function Y = A\. The open-collector outputs require pullup resistors to perform correctly. These outputs can be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOHlevels. The SN54ALS05A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS05A is characterized for operation from 0°C to 70°C.

SN54LS673, SN74LS673 The 'LS673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A three-state input/output (SER/Q15) port to the shift register allows serial entry and/or reading of data. The storage register is connected in a parallel data loop with the shift register and may be asynchronously cleared by taking the store-clear input low. The storage register may be parallel loaded with shift-register data to provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the storage-register data upon commmand. A high logic level at the chip-level (CS\) input disables both the shift-register clock and the storage register clock and places SER/Q15 in the high-impedance state. The store-clear function is not disabled by the chip select. Caution must be exercised to prevent false clocking of either the shift register or the storage register via the chip-select input. The shift clock should be low during the low-to-high transition of chip select and the store clock should be low during the high-to-low transition of chip select. SN54LS674, SN74LS674 The 'LS674 is a 16-bit parallel-in, serial-out shift register. A three-state input/output (SER/Q15) port provides access for entering a serial data or reading the shift-register word in a recirculating loop. The device has four basic modes of operation: Low-to-high-level changes at the chip select input should be made only when the clock input is low to prevent false clocking. SN54LS673, SN74LS673 The 'LS673 is a 16-bit shift register and a 16-bit storage register in a single 24-pin package. A three-state input/output (SER/Q15) port to the shift register allows serial entry and/or reading of data. The storage register is connected in a parallel data loop with the shift register and may be asynchronously cleared by taking the store-clear input low. The storage register may be parallel loaded with shift-register data to provide shift-register status via the parallel outputs. The shift register can be parallel loaded with the storage-register data upon commmand. A high logic level at the chip-level (CS\) input disables both the shift-register clock and the storage register clock and places SER/Q15 in the high-impedance state. The store-clear function is not disabled by the chip select. Caution must be exercised to prevent false clocking of either the shift register or the storage register via the chip-select input. The shift clock should be low during the low-to-high transition of chip select and the store clock should be low during the high-to-low transition of chip select. SN54LS674, SN74LS674 The 'LS674 is a 16-bit parallel-in, serial-out shift register. A three-state input/output (SER/Q15) port provides access for entering a serial data or reading the shift-register word in a recirculating loop. The device has four basic modes of operation: Low-to-high-level changes at the chip select input should be made only when the clock input is low to prevent false clocking.

These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select real-time or stored data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the recommended maximum IOLfor the -1 versions is increased to 48 mA. There are no -1 versions of the SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654. These devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable (OEAB and OEBA\) inputs are provided to control the transceiver functions. Select-control (SAB and SBA) inputs are provided to select real-time or stored data transfer. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. A low input level selects real-time data, and a high input level selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the octal bus transceivers and registers Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by simultaneously enabling OEAB and OEBA\. In this configuration, each output reinforces its input. When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state. The -1 versions of the SN74ALS651A and SN74ALS652A are identical to the standard versions except that the recommended maximum IOLfor the -1 versions is increased to 48 mA. There are no -1 versions of the SN54ALS652, SN54ALS653, SN74ALS653, and SN74ALS654.

Dual 4-Line To 1-Line Data Selectors/Multiplexers With 3-State Outputs

These identity comparators perform comparisons on two 8-bit binary or BCD words. The SN74ALS518 provides P = Q outputs, while the ´ALS520 and SN74ALS521 provide P = Q\ outputs. The SN74ALS518 has an open-collector output. The SN74ALS518 and ´ALS520 feature 20-k pullup resistors on the Q inputs for analog or switch data. The SN54ALS520 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS518, SN74ALS520, and SN74ALS521 are characterized for operation from 0°C to 70°C. These identity comparators perform comparisons on two 8-bit binary or BCD words. The SN74ALS518 provides P = Q outputs, while the ´ALS520 and SN74ALS521 provide P = Q\ outputs. The SN74ALS518 has an open-collector output. The SN74ALS518 and ´ALS520 feature 20-k pullup resistors on the Q inputs for analog or switch data. The SN54ALS520 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS518, SN74ALS520, and SN74ALS521 are characterized for operation from 0°C to 70°C.

These devices contain a single 8-input NAND gate. They perform the Boolean functionsorY = A\ + B\ + C\ + D\ + E\ + F\ + G\ + H\ in positive logic. The SN54F30 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F30 is characterized for operation from 0°C to 70°C. These devices contain a single 8-input NAND gate. They perform the Boolean functionsorY = A\ + B\ + C\ + D\ + E\ + F\ + G\ + H\ in positive logic. The SN54F30 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74F30 is characterized for operation from 0°C to 70°C.

These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear () and enable (G\) inputs as shown in the function table. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G\ should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. The SN54ALS259 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS259 is characterized for operation from 0°C to 70°C. These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs. Four distinct modes of operation are selectable by controlling the clear () and enable (G\) inputs as shown in the function table. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G\ should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs. The SN54ALS259 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS259 is characterized for operation from 0°C to 70°C.

These devices contain six independent noninverting buffers. They perform the Boolean function Y = A. The open-collector outputs require pullup resistors to perform correctly. They can be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOHlevels. These devices contain six independent noninverting buffers. They perform the Boolean function Y = A. The open-collector outputs require pullup resistors to perform correctly. They can be connected to other open-collector outputs to implement active-low wired-OR or active-high wired-AND functions. Open-collector devices are often used to generate higher VOHlevels.

High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs