The UCD7230A is one in the UCD7k family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. The UCD7230A is a MOSFET gate driver specifically designed for synchronous buck applications. It is ideally suited to provide the bridge between digital controllers such as the UCD91xx or the UCD92xx and the power stage. With cycle-by-cycle current limit protection, the UCD7230A device protects the power stage from faulty input signals or excessive load currents. The UCD7230A includes high-side and low-side gate drivers which utilize Texas Instrument’s TrueDrive output architecture. This architecture delivers rated current into the gate capacitance of a MOSFET during the Miller plateau region of the switching. Furthermore, the UCD7230A offers a low offset differential amplifier with a fixed gain of 48. This amplifier greatly simplifies the task of conditioning small current sense signals inherent in high efficiency buck converters. The UCD7230A includes a 3.3-V, 10-mA linear regulator to provide power to digital controllers such as the UCD91xx. The UCD7230A is compatible with standard 3.3-V I/O ports of the UCD91xx, the TMS320™ family DSPs, microprocessors, or ASICs. The UCD7230A is offered in the space-saving QFN package. Package pin out has been carefully designed for optimal board layout The UCD7230A is one in the UCD7k family of digital control compatible drivers for applications utilizing digital control techniques or applications requiring fast local peak current limit protection. The UCD7230A is a MOSFET gate driver specifically designed for synchronous buck applications. It is ideally suited to provide the bridge between digital controllers such as the UCD91xx or the UCD92xx and the power stage. With cycle-by-cycle current limit protection, the UCD7230A device protects the power stage from faulty input signals or excessive load currents. The UCD7230A includes high-side and low-side gate drivers which utilize Texas Instrument’s TrueDrive output architecture. This architecture delivers rated current into the gate capacitance of a MOSFET during the Miller plateau region of the switching. Furthermore, the UCD7230A offers a low offset differential amplifier with a fixed gain of 48. This amplifier greatly simplifies the task of conditioning small current sense signals inherent in high efficiency buck converters. The UCD7230A includes a 3.3-V, 10-mA linear regulator to provide power to digital controllers such as the UCD91xx. The UCD7230A is compatible with standard 3.3-V I/O ports of the UCD91xx, the TMS320™ family DSPs, microprocessors, or ASICs. The UCD7230A is offered in the space-saving QFN package. Package pin out has been carefully designed for optimal board layout

The UCD7231 high current driver is specifically designed for digitally-controlled, point-of-load, synchronous buck switching power supplies. Two driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven to +6 V by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply their own gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 to 15 V. Internal under voltage lockout (UVLO) logic insures VGGis good before allowing chip operation. A drive logic block allows operation in one of two modes selected by the SRE Mode pin. In Synchronous Mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is automatically adjusted to prevent cross conduction. The Synchronous Rectifier Enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. In Independent Mode, the PWM and SRE pins control the high-side and low-side gates directly. No anti-cross-conduction logic is used in this mode. On-board comparators monitor the voltage across the high side switch and the voltage across an external current sense element to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the event of a high-side fault or an over-current fault, the high-side FET turned off and the Fault Flag (FLT) is asserted to alert the digital controller. The fault thresholds are independently set by the HS Sense and ILIM pins. Output current is measured and monitored by a precision, high gain, switched capacitor differential amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the digital controller on the IMONpin. The current sense amplifier has output offset of 0.5 V so that both positive (sourcing) and negative (sinking) current can be sensed. An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault automatically clears when the die temperatures falls by approximately 20°. The UCD7231 high current driver is specifically designed for digitally-controlled, point-of-load, synchronous buck switching power supplies. Two driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven to +6 V by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply their own gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 to 15 V. Internal under voltage lockout (UVLO) logic insures VGGis good before allowing chip operation. A drive logic block allows operation in one of two modes selected by the SRE Mode pin. In Synchronous Mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is automatically adjusted to prevent cross conduction. The Synchronous Rectifier Enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. In Independent Mode, the PWM and SRE pins control the high-side and low-side gates directly. No anti-cross-conduction logic is used in this mode. On-board comparators monitor the voltage across the high side switch and the voltage across an external current sense element to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the event of a high-side fault or an over-current fault, the high-side FET turned off and the Fault Flag (FLT) is asserted to alert the digital controller. The fault thresholds are independently set by the HS Sense and ILIM pins. Output current is measured and monitored by a precision, high gain, switched capacitor differential amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the digital controller on the IMONpin. The current sense amplifier has output offset of 0.5 V so that both positive (sourcing) and negative (sinking) current can be sensed. An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault automatically clears when the die temperatures falls by approximately 20°.

The UCD7232 high current driver is specifically designed for digitally-controlled, point-of-load, synchronous buck switching power supplies. Two driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply their own gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 to 15 V. Internal under voltage lockout (UVLO) logic insures VGGis good before allowing chip operation. A drive logic block allows operation in one of two modes selected by the SRE Mode pin. In Synchronous Mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is automatically adjusted to prevent cross conduction. The Synchronous Rectifier Enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. In Independent Mode, the PWM and SRE pins control the high-side and low-side gates directly. No anti-cross-conduction logic is used in this mode. On-board comparators monitor the voltage across the high side switch and the voltage across an external current sense element to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the event of a high-side fault or an over-current fault, the high-side FET turned off and the Fault Flag (FLT) is asserted to alert the digital controller. The fault thresholds are independently set by the HS Sense and ILIM pins. Output current is measured and monitored by a precision, high gain, switched capacitor differential amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the digital controller on the IMONpin. The current sense amplifier has output offset of 0.5 V so that both positive (sourcing) and negative (sinking) current can be sensed. An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault automatically clears when the die temperatures falls by approximately 207°. The UCD7232 high current driver is specifically designed for digitally-controlled, point-of-load, synchronous buck switching power supplies. Two driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply their own gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 to 15 V. Internal under voltage lockout (UVLO) logic insures VGGis good before allowing chip operation. A drive logic block allows operation in one of two modes selected by the SRE Mode pin. In Synchronous Mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is automatically adjusted to prevent cross conduction. The Synchronous Rectifier Enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. In Independent Mode, the PWM and SRE pins control the high-side and low-side gates directly. No anti-cross-conduction logic is used in this mode. On-board comparators monitor the voltage across the high side switch and the voltage across an external current sense element to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the event of a high-side fault or an over-current fault, the high-side FET turned off and the Fault Flag (FLT) is asserted to alert the digital controller. The fault thresholds are independently set by the HS Sense and ILIM pins. Output current is measured and monitored by a precision, high gain, switched capacitor differential amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the digital controller on the IMONpin. The current sense amplifier has output offset of 0.5 V so that both positive (sourcing) and negative (sinking) current can be sensed. An on-chip temperature sense monitors the die temperature. If it exceeds approximately 165°C, the temperature sensor will initiate a thermal shutdown that halts output switching and sets the FLT flag. The temperature fault automatically clears when the die temperatures falls by approximately 207°.

The UCD7242 is a complete power system ready to drive two independent buck power supplies. High side MOSFETs, low side MOSFETs, drivers, current sensing circuitry and necessary protection functions are all integrated into one monolithic solution to facilitate minimum size and maximum efficiency. Driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven to +6.25 V by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply an independent gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2V to 18V. Internal under voltage lockout (UVLO) logic ensures VGGis good before allowing chip operation. The synchronous rectifier enable (SRE) pin controls whether or not the low-side MOSFET is turned on when the PWM signal is low. When SRE is high the part operates in continuous conduction mode for all loads. In this mode the drive logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is also optimized to prevent cross conduction. When SRE is low, the part operates in discontinuous conduction mode at light loads. In this mode the low-side MOSFET is always held off. On-board comparators monitor the current through the high side switch to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator to avoid false reports coincident with switching edge noise. In the event of an over-current fault, the high-side FET is turned off and the Fault Flag (FLT) is asserted to alert the controller. MOSFET current is measured and monitored by a precision integrated current sense element. This method provides an accuracy of ±5% over most of the load range. The amplified signal is available for use by the controller on the IMONpin. An on-chip temperature sense converts the die temperature to a voltage at the TMONpin for the controller’s use. If the die temperature exceeds 170°C, the temperature sensor initiates a thermal shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die temperature falls below the thermal hysteresis band. The UCD7242 is a complete power system ready to drive two independent buck power supplies. High side MOSFETs, low side MOSFETs, drivers, current sensing circuitry and necessary protection functions are all integrated into one monolithic solution to facilitate minimum size and maximum efficiency. Driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven to +6.25 V by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply an independent gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2V to 18V. Internal under voltage lockout (UVLO) logic ensures VGGis good before allowing chip operation. The synchronous rectifier enable (SRE) pin controls whether or not the low-side MOSFET is turned on when the PWM signal is low. When SRE is high the part operates in continuous conduction mode for all loads. In this mode the drive logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is also optimized to prevent cross conduction. When SRE is low, the part operates in discontinuous conduction mode at light loads. In this mode the low-side MOSFET is always held off. On-board comparators monitor the current through the high side switch to safeguard the power stage from sudden high current loads. Blanking delay is set for the high side comparator to avoid false reports coincident with switching edge noise. In the event of an over-current fault, the high-side FET is turned off and the Fault Flag (FLT) is asserted to alert the controller. MOSFET current is measured and monitored by a precision integrated current sense element. This method provides an accuracy of ±5% over most of the load range. The amplified signal is available for use by the controller on the IMONpin. An on-chip temperature sense converts the die temperature to a voltage at the TMONpin for the controller’s use. If the die temperature exceeds 170°C, the temperature sensor initiates a thermal shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die temperature falls below the thermal hysteresis band.

The UCD74106 is a complete power system ready to drive a buck power supply (). High-side MOSFETs, low-side MOSFETs, drivers, current sensing circuitry and necessary protection functions are all integrated into one monolithic solution to facilitate minimum size and maximum efficiency. Driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven to 6.25 V by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply an independent gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 V to 18 V. Internal Under Voltage Lockout (UVLO) logic insures VGGis good before allowing chip operation. A drive logic block allows operation in one of two modes. In synchronous mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is optimized to prevent cross conduction. The synchronous rectifier enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low. The UCD74106 is a complete power system ready to drive a buck power supply (). High-side MOSFETs, low-side MOSFETs, drivers, current sensing circuitry and necessary protection functions are all integrated into one monolithic solution to facilitate minimum size and maximum efficiency. Driver circuits provide high charge and discharge current for the high-side NMOS switch and the low-side NMOS synchronous rectifier in a synchronous buck circuit. The MOSFET gates are driven to 6.25 V by an internally regulated VGGsupply. The internal VGGregulator can be disabled to permit the user to supply an independent gate drive voltage. This flexibility allows a wide power conversion input voltage range of 2.2 V to 18 V. Internal Under Voltage Lockout (UVLO) logic insures VGGis good before allowing chip operation. A drive logic block allows operation in one of two modes. In synchronous mode, the logic block uses the PWM signal to control both the high-side and low-side gate drive signals. Dead time is optimized to prevent cross conduction. The synchronous rectifier enable (SRE) pin controls whether or not the low-side FET is turned on when the PWM signal is low.

UCD74111 is a multi-chip module integrating a driver device and two NexFET power MOSFETs into a thermally enhanced compact, 5 mm × 7 mm, QFN package. A 15-A output current capability makes the device suitable for powering DSP and ASIC. The device is designed to complement digital or analog PWM controllers. The PWM input of the driver device is 3-state compatible. Two driver circuits provide high charge and discharge current for the high-side N-channel FET switch and the low-side N-channel FET synchronous rectifier in a synchronous buck converter. A precision current sensing amplifier that processes the voltage present across an external current sense element measures and monitors the output current. The PWM controller on the IMON pin can use this amplified signal. On-board comparators monitor the voltage across the high-side switch and the voltage across the external current sense element to safeguard the power stage from sudden high-current loads. A single resistor for the high-side comparator sets the blanking delay. This delay guards against false reports coincident with switching edge noise. In the event of a high-side fault or an overcurrent fault, the high-side FET turns OFF and the fault flag (FLT) asserts to alert the PWM controller. UCD74111 is a multi-chip module integrating a driver device and two NexFET power MOSFETs into a thermally enhanced compact, 5 mm × 7 mm, QFN package. A 15-A output current capability makes the device suitable for powering DSP and ASIC. The device is designed to complement digital or analog PWM controllers. The PWM input of the driver device is 3-state compatible. Two driver circuits provide high charge and discharge current for the high-side N-channel FET switch and the low-side N-channel FET synchronous rectifier in a synchronous buck converter. A precision current sensing amplifier that processes the voltage present across an external current sense element measures and monitors the output current. The PWM controller on the IMON pin can use this amplified signal. On-board comparators monitor the voltage across the high-side switch and the voltage across the external current sense element to safeguard the power stage from sudden high-current loads. A single resistor for the high-side comparator sets the blanking delay. This delay guards against false reports coincident with switching edge noise. In the event of a high-side fault or an overcurrent fault, the high-side FET turns OFF and the fault flag (FLT) asserts to alert the PWM controller.

UCD74120 is a multi-chip module integrating a driver device and two NexFET power MOSFETs into a thermally enhanced compact, 5 mm × 7 mm, QFN package. A 25-A output current capability makes the device suitable for powering DSP and ASIC. The device is designed to complement digital or analog PWM controllers. The PWM input of the driver device is 3-state compatible. Two driver circuits provide high charge and discharge current for the high-side N-channel FET switch and the low-side N-channel FET synchronous rectifier in a synchronous buck converter. Output current is measured and monitored by a precision current sensing amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the PWM controller on the IMON pin. On-board comparators monitor the voltage across the high-side switch and the voltage across the external current sense element to safeguard the power stage from sudden high-current loads. Blanking delay is set for the high-side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the even of a high-side fault or an overcurrent fault, the high-side FET is turned off and the fault flag (FLT) is asserted to alert the PWM controller. UCD74120 is a multi-chip module integrating a driver device and two NexFET power MOSFETs into a thermally enhanced compact, 5 mm × 7 mm, QFN package. A 25-A output current capability makes the device suitable for powering DSP and ASIC. The device is designed to complement digital or analog PWM controllers. The PWM input of the driver device is 3-state compatible. Two driver circuits provide high charge and discharge current for the high-side N-channel FET switch and the low-side N-channel FET synchronous rectifier in a synchronous buck converter. Output current is measured and monitored by a precision current sensing amplifier that processes the voltage present across an external current sense element. The amplified signal is available for use by the PWM controller on the IMON pin. On-board comparators monitor the voltage across the high-side switch and the voltage across the external current sense element to safeguard the power stage from sudden high-current loads. Blanking delay is set for the high-side comparator by a single resistor in order to avoid false reports coincident with switching edge noise. In the even of a high-side fault or an overcurrent fault, the high-side FET is turned off and the fault flag (FLT) is asserted to alert the PWM controller.

The UCD8220-Q1 analog pulse-width modulator (PWM) device is used in digitally managed power supplies using a microcontroller or the TMS320 DSP family. The UCD8220-Q1 device is a double-ended PWM controller configured with push-pull drive logic. Systems using the UCD8220-Q1 device close the PWM feedback loop with traditional analog methods, but the UCD8220-Q1 controller includes circuitry to interpret a time-domain digital pulse train. The pulse train contains the operating frequency and maximum duty cycle limit which are used to control the power supply operation. The device circuitry eases implementation of a converter with high level control features without the added complexity or possible PWM resolution limitations of closing the control loop in the discrete time domain. The UCD8220-Q1 device can be configured for either peak current mode or voltage mode control. The device provides a programmable current-limit function and a digital output current-limit flag which can be monitored by the host controller to set the current limit operation. For fast switching speeds, the output stage uses the TrueDrive output circuit architecture, which delivers rated current of ±4-A into the gate of a MOSFET. Finally the device also includes a 3.3-V, 10-mA linear regulator to provide power to the digital controller or act as a reference in the system. The UCD8220-Q1 controller is compatible with the standard 3.3-V I/O ports of UCD9K digital power controllers, DSPs, microcontrollers, or ASICs and is offered in the PowerPAD™ integrated circuit package HTSSOP. The UCD8220-Q1 analog pulse-width modulator (PWM) device is used in digitally managed power supplies using a microcontroller or the TMS320 DSP family. The UCD8220-Q1 device is a double-ended PWM controller configured with push-pull drive logic. Systems using the UCD8220-Q1 device close the PWM feedback loop with traditional analog methods, but the UCD8220-Q1 controller includes circuitry to interpret a time-domain digital pulse train. The pulse train contains the operating frequency and maximum duty cycle limit which are used to control the power supply operation. The device circuitry eases implementation of a converter with high level control features without the added complexity or possible PWM resolution limitations of closing the control loop in the discrete time domain. The UCD8220-Q1 device can be configured for either peak current mode or voltage mode control. The device provides a programmable current-limit function and a digital output current-limit flag which can be monitored by the host controller to set the current limit operation. For fast switching speeds, the output stage uses the TrueDrive output circuit architecture, which delivers rated current of ±4-A into the gate of a MOSFET. Finally the device also includes a 3.3-V, 10-mA linear regulator to provide power to the digital controller or act as a reference in the system. The UCD8220-Q1 controller is compatible with the standard 3.3-V I/O ports of UCD9K digital power controllers, DSPs, microcontrollers, or ASICs and is offered in the PowerPAD™ integrated circuit package HTSSOP.

The UCD90120A is a 12-rail PMBus/I2C addressable power-supply sequencer and monitor. The device integrates a 12-bit ADC for monitoring up to 12 power-supply voltage inputs. Twenty-six GPIO pins can be used for power supply enables, power-on reset signals, external interrupts, cascading, or other system functions. Twelve of these pins offer PWM functionality. Using these pins, the UCD90120A offers support for margining, and general-purpose PWM functions. Specific power states can be achieved using the Pin-Selected Rail States feature. This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used for hardware devices. The TI Fusion Digital Power™ designer software is provided for device configuration. This PC-based graphical user interface (GUI) offers an intuitive interface for configuring, storing, and monitoring all system operating parameters. The UCD90120A is a 12-rail PMBus/I2C addressable power-supply sequencer and monitor. The device integrates a 12-bit ADC for monitoring up to 12 power-supply voltage inputs. Twenty-six GPIO pins can be used for power supply enables, power-on reset signals, external interrupts, cascading, or other system functions. Twelve of these pins offer PWM functionality. Using these pins, the UCD90120A offers support for margining, and general-purpose PWM functions. Specific power states can be achieved using the Pin-Selected Rail States feature. This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used for hardware devices. The TI Fusion Digital Power™ designer software is provided for device configuration. This PC-based graphical user interface (GUI) offers an intuitive interface for configuring, storing, and monitoring all system operating parameters.