5962-86816018-Bit Shift Registers With 3-State Output Registers | Integrated Circuits (ICs) | 1 | Active | The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state.
The SNx4HC595 devices contain an 8-bit, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. |
| Shift Registers | 2 | Active | These 4-bit registers feature parallel inputs, parallel outputs, J-Kserial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QAand QD).
Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-Kinputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.
The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C.
These 4-bit registers feature parallel inputs, parallel outputs, J-Kserial inputs, shift/load control input, and a direct overriding clear. The registers have two modes of operation: parallel (broadside) load, and shift (in the direction QAand QD).
Parallel loading is accomplished by applying the 4-bits of data and taking the shift/load control input low. The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input. During loading, serial data flow is inhibited.
Shifting is accomplished synchronously when the shift/load control input is high. Serial data for this mode is entered at the J-Kinputs. These inputs permit the first stage to perform as a J-K, D, or T type flip-flop as shown in the function table.
The SN54HC195 is characterized for operation over the full military temperature range of –55°C to 125°C. |
| Buffers, Drivers, Receivers, Transceivers | 1 | Active | These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receviers and transmitters. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical G (active-low control) inputs.
The SN54HC' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74HC' family is characterized for operation from -40°C to 85°C.
These Hex buffers and line drivers are designed specifically to improve both the performance and density of three-state memory address drivers, clock drivers, and bus-oriented receviers and transmitters. The designer has a choice of selected combinations of inverting and noninverting outputs, symmetrical G (active-low control) inputs.
The SN54HC' family is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74HC' family is characterized for operation from -40°C to 85°C. |
5962-8683701Military single 8-input, 4.5-V to 5.5-V bipolar NAND gate | Integrated Circuits (ICs) | 2 | Active | These devices contain an 8-input positive-NAND gate and perform the following Boolean functions in positive logic:
Y =A • B •C • D • E • F • G • H
or
Y =A+B+C+D+E+F+G
These devices contain an 8-input positive-NAND gate and perform the following Boolean functions in positive logic:
Y =A • B •C • D • E • F • G • H
or
Y =A+B+C+D+E+F+G |
5962-86838012Military 3-ch, 3-input, 4.5-V to 5.5-V bipolar NOR gates | Gates and Inverters | 1 | Active | These devices contain three independent 3-input positive-NOR gates. They perform the Boolean functionsorin positive logic.
The SN54ALS27A and SN54AS27 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS27A and SN74AS27 are characterized for operation from 0°C to 70°C.
These devices contain three independent 3-input positive-NOR gates. They perform the Boolean functionsorin positive logic.
The SN54ALS27A and SN54AS27 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS27A and SN74AS27 are characterized for operation from 0°C to 70°C. |
5962-86839012Military 8-ch, 4.5-V to 5.5-V bipolar buffers with 3-state outputs | Buffers, Drivers, Receivers, Transceivers | 3 | Active | These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs.
The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS244C.
The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C.
These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE andinputs.
The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOLfor the -1 version is 48 mA. There is no -1 version of the SN54ALS244C.
The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C. |
5962-8684201Military, 4-ch, 2-input, 4.5-V to 5.5-V ultra-high-speed (4 ns) bipolar AND gate | Gates and Inverters | 1 | Active | These devices contain four independent 2-input positive-AND gates. They perform the Boolean functions Y = A \x95 B orin positive logic.
The SN54ALS08 and SN54AS08 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS08 and SN74AS08 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input positive-AND gates. They perform the Boolean functions Y = A \x95 B orin positive logic.
The SN54ALS08 and SN54AS08 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS08 and SN74AS08 are characterized for operation from 0°C to 70°C. |
5962-86842012Space, 4-ch, 2-input, 4.5-V to 5.5-V 16-mA drive strength bipolar OR gate with TTL-compatible inputs | Specialty Logic | 310 | Active | These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform.
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QAoutput. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input.
'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform.
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QAoutput. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input.
'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times. |
5962-86844012Military 4-ch, 2-input, 4.5-V to 5.5-V bipolar NOR gates | Logic | 1 | Active | These devices contain four independent 2-input positive-NOR gates. They perform the Boolean functionsor Y = A\ \x95 B\ in positive logic.
The SN54ALS02A and SN54AS02 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS02A and SN74AS02 are characterized for operation from 0°C to 70°C.
These devices contain four independent 2-input positive-NOR gates. They perform the Boolean functionsor Y = A\ \x95 B\ in positive logic.
The SN54ALS02A and SN54AS02 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS02A and SN74AS02 are characterized for operation from 0°C to 70°C. |
5962-8685201Military, 4-ch 2-input 4.5-V to 5.5-V OR gate with TTL-compatible inputs | Integrated Circuits (ICs) | 1 | Active | This device contains four independent 2-input OR gates. Each gate performs the Boolean function Y = A + B in positive logic.
This device contains four independent 2-input OR gates. Each gate performs the Boolean function Y = A + B in positive logic. |
