| Logic | 6 | Active | |
| Signal Switches, Multiplexers, Decoders | 3 | Obsolete | |
74ALS873Dual 4-Bit D-Type Latches With 3-State Outputs | Logic | 3 | Active | These dual 4-bit D-type latches feature 3-state outputs designed specifically for bus driving. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The dual 4-bit latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs in true form, according to the function table. When LE is low, the outputs are latched. When the clear () input goes low, the Q outputs go low independently of LE. The outputs are in the high-impedance state when the output-enable () input is at a high logic level.
The SN54ALS873B and SN54AS873A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS873B and SN74AS873A are characterized for operation from 0°C to 70°C.
These dual 4-bit D-type latches feature 3-state outputs designed specifically for bus driving. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The dual 4-bit latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs in true form, according to the function table. When LE is low, the outputs are latched. When the clear () input goes low, the Q outputs go low independently of LE. The outputs are in the high-impedance state when the output-enable () input is at a high logic level.
The SN54ALS873B and SN54AS873A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS873B and SN74AS873A are characterized for operation from 0°C to 70°C. |
74ALS874Dual 4-Bit D-Type Edge-Triggered Flip-Flops With 3-State Outputs | Flip Flops | 5 | Active | These dual 4-bit D-type edge-triggered flip-flops feature 3-state outputs designed specifically as bus drivers. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The edge-triggered flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN54ALS874B, SN74ALS874B, and SN74AS874 have clear () inputs and noninverting Q outputs. The SN74ALS876A and SN74AS876 have preset () inputs and inverting Q\ outputs; takinglow causes the four Q or Q\ outputs to go low independently of the clock.
The SN54ALS874B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS874B, SN74ALS876A, SN74AS874, and SN74AS876 devices are characterized for operation from 0°C to 70°C.
These dual 4-bit D-type edge-triggered flip-flops feature 3-state outputs designed specifically as bus drivers. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
The edge-triggered flip-flops enter data on the low-to-high transition of the clock (CLK) input. The SN54ALS874B, SN74ALS874B, and SN74AS874 have clear () inputs and noninverting Q outputs. The SN74ALS876A and SN74AS876 have preset () inputs and inverting Q\ outputs; takinglow causes the four Q or Q\ outputs to go low independently of the clock.
The SN54ALS874B is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS874B, SN74ALS876A, SN74AS874, and SN74AS876 devices are characterized for operation from 0°C to 70°C. |
| Integrated Circuits (ICs) | 3 | Obsolete | |
74ALS990Octal D-Type Transparent Read-Back Latches | Integrated Circuits (ICs) | 4 | Active | This 8-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus.
The eight latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
Read back is provided through the output-enable () input. Whenis taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. Whenis taken high, the output of the data latches is isolated from the D inputs.does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict.
The SN74ALS990 is characterized for operation from 0°C to 70°C.
This 8-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus.
The eight latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
Read back is provided through the output-enable () input. Whenis taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. Whenis taken high, the output of the data latches is isolated from the D inputs.does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict.
The SN74ALS990 is characterized for operation from 0°C to 70°C. |
74ALS9929-Bit D-Type Transparent Read-Back Latches With 3-State Outputs | Buffers, Drivers, Receivers, Transceivers | 5 | Active | This 9-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. In addition, this device provides a 3-state buffer-type output and is easily implemented in parity applications.
The nine latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. The Q outputs are in the 3-state condition when the output-enable () input is high.
Read back is provided through the output-enable () input. Whenis taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. Whenis taken high, the output of the data latches is isolated from the D inputs.does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict.
The SN74ALS992 is characterized for operation from 0°C to 70°C.
This 9-bit latch is designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. In addition, this device provides a 3-state buffer-type output and is easily implemented in parity applications.
The nine latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. The Q outputs are in the 3-state condition when the output-enable () input is high.
Read back is provided through the output-enable () input. Whenis taken low, the data present at the output of the data latches is allowed to pass back onto the input data bus. Whenis taken high, the output of the data latches is isolated from the D inputs.does not affect the internal operation of the latches; however, precautions should be taken not to create a bus conflict.
The SN74ALS992 is characterized for operation from 0°C to 70°C. |
| Logic | 2 | Obsolete | |
74ALS996Octal D-Type Edge-Triggered Read-Back Latches | Buffers, Drivers, Receivers, Transceivers | 6 | Active | These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable () input is low. Data can be read back onto the data inputs by taking the read () input low, in addition to havinglow. When EN\ is high, both the read-back and write modes are disabled. Transitions onshould only be made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by the polarity (T/C\) input. When T/C\ is high, Q is the same as is stored in the flip-flops. When T/C\ is low, the output data is inverted. The Q outputs can be placed in the high-impedance state by taking the output-enable () input high.does not affect the internal operation of the register. Old data can be retained or new data can be entered while the outputs are off.
A low level at the clear () input resets the internal registers low. The clear function is asynchronous and overrides all other register functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum IOLfor the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
The SN54ALS996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS996 is characterized for operation from 0°C to 70°C.
These 8-bit latches are designed specifically for storing the contents of the input data bus and providing the capability of reading back the stored data onto the input data bus. The Q outputs are designed with bus-driving capability.
The edge-triggered flip-flops enter the data on the low-to-high transition of the clock (CLK) input when the enable () input is low. Data can be read back onto the data inputs by taking the read () input low, in addition to havinglow. When EN\ is high, both the read-back and write modes are disabled. Transitions onshould only be made with CLK high to prevent false clocking.
The polarity of the Q outputs can be controlled by the polarity (T/C\) input. When T/C\ is high, Q is the same as is stored in the flip-flops. When T/C\ is low, the output data is inverted. The Q outputs can be placed in the high-impedance state by taking the output-enable () input high.does not affect the internal operation of the register. Old data can be retained or new data can be entered while the outputs are off.
A low level at the clear () input resets the internal registers low. The clear function is asynchronous and overrides all other register functions.
The -1 version of the SN74ALS996 is identical to the standard version, except that the recommended maximum IOLfor the -1 version is increased to 48 mA. There is no -1 version of the SN54ALS996.
The SN54ALS996 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS996 is characterized for operation from 0°C to 70°C. |
74ALVC00Enhanced product 4-ch, 2-input, 1.65-V to 3.6-V NAND gates | Logic | 10 | Active | The SN74ALVC00 quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCCoperation.
The device performs the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic.
The SN74ALVC00 quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCCoperation.
The device performs the Boolean function Y = (A • B)\ or Y = A\ + B\ in positive logic. |
