Texas Instruments

These devices contain six independent inverters. These devices contain six independent inverters.

These TTL hex buffers and drivers feature high-voltage open-collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are characterized for use as buffers for driving TTL inputs. The SN5407 and SN7407 devices have minimum breakdown voltages of 30 V, and the SN5417 and SN7417 devices have minimum breakdown voltages of 15 V. The maximum sink current is 30 mA for the SN5407 and SN5417 devices and 40 mA for the SN7407 and SN7417 devices. These devices perform the Boolean function Y = A in positive logic. These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average propagation delay time is 14 ns. These TTL hex buffers and drivers feature high-voltage open-collector outputs for interfacing with high-level circuits (such as MOS) or for driving high-current loads (such as lamps or relays), and also are characterized for use as buffers for driving TTL inputs. The SN5407 and SN7407 devices have minimum breakdown voltages of 30 V, and the SN5417 and SN7417 devices have minimum breakdown voltages of 15 V. The maximum sink current is 30 mA for the SN5407 and SN5417 devices and 40 mA for the SN7407 and SN7417 devices. These devices perform the Boolean function Y = A in positive logic. These circuits are completely compatible with most TTL families. Inputs are diode clamped to minimize transmission-line effects, which simplifies design. Typical power dissipation is 145 mW, and average propagation delay time is 14 ns.

These multivibrators feature dual negative-transition-triggered inputs and a single positive-transition-triggered input which can be used as an inhibit input. Complementary output pulses are provided. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for the B input allow jitter-free triggering from inputs with transition rates as slow as 1 volt/second, providing the circuit with an excellent noise immunity of typically 1.2 volts. A high immunity to VCCnoise of typically 1.5 volts is also provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the inputs and are a function only of the timing components. Input pulses may be of any duration relative to the output puls. Output pulse length may be varied from 40 nanoseconds to 28 seconds by choosing appropriate timing components. With no external timing components (i.e., Rintconnected to VCC, Cextand Rext/Cextopen), an output pulse of typically 30 or 35 nanoseconds is achieved which may be used as a d-c triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Pulse width stability is achieved through internal compensation and is virtually independent of VCCand temperature. In most application, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCCranges for more than six decades of timing capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kmay be used. Also, the range of jitter-free output pulse widths is extended if VCCis held to 5 volts and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed. These multivibrators feature dual negative-transition-triggered inputs and a single positive-transition-triggered input which can be used as an inhibit input. Complementary output pulses are provided. Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input pulse. Schmitt-trigger input circuitry (TTL hysteresis) for the B input allow jitter-free triggering from inputs with transition rates as slow as 1 volt/second, providing the circuit with an excellent noise immunity of typically 1.2 volts. A high immunity to VCCnoise of typically 1.5 volts is also provided by internal latching circuitry. Once fired, the outputs are independent of further transitions of the inputs and are a function only of the timing components. Input pulses may be of any duration relative to the output puls. Output pulse length may be varied from 40 nanoseconds to 28 seconds by choosing appropriate timing components. With no external timing components (i.e., Rintconnected to VCC, Cextand Rext/Cextopen), an output pulse of typically 30 or 35 nanoseconds is achieved which may be used as a d-c triggered reset signal. Output rise and fall times are TTL compatible and independent of pulse length. Pulse width stability is achieved through internal compensation and is virtually independent of VCCand temperature. In most application, pulse stability will only be limited by the accuracy of external timing components. Jitter-free operation is maintained over the full temperature and VCCranges for more than six decades of timing capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kmay be used. Also, the range of jitter-free output pulse widths is extended if VCCis held to 5 volts and free-air temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher duty cycles are available if a certain amount of pulse-width jitter is allowed.