STM32WLE5JCSub-GHz Wireless Microcontrollers. Arm Cortex-M4 @48 MHz with 256 Kbytes of Flash memory, 64 Kbytes of SRAM. LoRa, (G)FSK, (G)MSK, BPSK modulations. AES 256-bit. Multiprotocol System-on-Chip. | RF Transceiver ICs | 2 | Active | The STM32WLE5/E4xx long-range wireless and ultra-low-power devices embed a powerful and ultra-low-power LPWAN-compliant radio solution, enabling the following modulations: LoRa®, (G)FSK, (G)MSK, and BPSK.
The LoRa®modulation is available in STM32WLx5xx only.
These devices are designed to be extremely low-power and are based on the high-performance Arm®Cortex®-M4 32-bit RISC core operating at a frequency of up to 48 MHz. This core implements a full set of DSP instructions and an independent memory protection unit (MPU) that enhances the application security.
The devices embed high-speed memories (flash memory up to 256 Kbytes, SRAM up to 64 Kbytes), and an extensive range of enhanced I/Os and peripherals.
The devices also embed several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection and proprietary code readout protection.
These devices offer a 12-bit ADC, a 12-bit DAC low-power sample-and-hold, two ultra-low-power comparators associated with a high-accuracy reference voltage generator.
The devices embed a low-power RTC with a 32-bit sub-second wakeup counter, one 16-bit single-channel timer, two 16-bit four-channel timers (supporting motor control), one 32-bit four-channel timer and three 16-bit ultra-low-power timers.
These devices also embed two DMA controllers (7 channels each) allowing any transfer combination between memory (flash memory, SRAM1 and SRAM2) and peripheral, using the DMAMUX1 for flexible DMA channel mapping.
The devices also feature the following standard and advanced communication interfaces:two USARTs (supporting LIN, smartcard, IrDA, modem control and ISO7816), one low-power UART (LPUART), three I2Cs (SMBus/PMBus), two SPIs (up to 16 MHz, one supporting I2S), semaphores for processor firmware process synchronization.
The operating temperature/voltage ranges are –40 °C to +105 °C (+85 °C with radio) from a 1.8 V to 3.6 V power supply. A comprehensive set of power-saving modes allows the design of low-power applications.
The devices integrate a high-efficiency SMPS step-down converter and independent power supplies for ADC, DAC and comparator analog inputs.
A VBATdedicated supply allows the LSE 32.768 kHz oscillator, the RTC and the backup registers to be backed up. The devices can maintain these functions even if the main VDDis not present, through a CR2032-like battery, a supercap or a small rechargeable battery. |
STM6315Open drain microprocessor reset | PMIC | 7 | Active | The STM6315 Microprocessor Reset Circuit is a low power supervisory device used to monitor power supplies. It performs a single function: asserting a reset signal whenever the VCCsupply voltage drops below a preset value and keeping it asserted until VCChas risen above the preset threshold for a minimum period of time (trec). It also provides a manual reset input (MR). The open drainRSToutput can be pulled up to a voltage higher than VCC, but less than 6V.
The STM6315 comes with standard factory-trimmed reset thresholds of 2.63V, 2.93V, 3.08V, 4.38V, and 4.63V. The STM6315 is available in the SOT143-4 package. |
| PMIC | 6 | Active | |
STM63225-pin supervisor with watchdog timer and push-button reset | PMIC | 5 | Active | The STM6xxx supervisors are self-contained devices which provide microprocessor supervisory functions. A precision voltage reference and comparator monitors the VCCinput for an out-of-tolerance condition. When an invalid VCCcondition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM6322/6825) and/or a push-button (MR) reset input.
These devices are available in a standard 5-pin SOT23 package. |
| Integrated Circuits (ICs) | 3 | Active | |
STM6505Dual push-button Smart Reset with user-adjustable setup delays | Power Management (PMIC) | 2 | Active | STM6502 has two combined Smart Reset inputs (SR0andSR1) with delayed Smart Reset setup time (tSRC) programmed by an external capacitor on the SRC pin.
STM6503 is similar to STM6502, has two combined delayed Smart Reset inputs (SR0,SR1) and three user-selectable delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s through a three-state TSR input pin: when connected to ground, tSRC= 2 s; when left open, tSRC= 6 s; when connected to VCC, tSRC= 10 s (all the times are minimum).
STM6504 has two independent Smart Reset inputs.SR0provides the delayed Smart Reset setup time (tSRC) function with three user-selectable tSRCoptions through a three-state TSR input pin: when connected to ground, tSRC= 2 s; when left open, tSRC= 6 s; when connected to VCC, tSRC= 10 s (all the times are minimum). SRE provides instant reset. SRE is edge-triggered with a special debounce time (tDEBOUNCE= 240 ms min.) at the falling edge after a valid reset period.
STM6505 has two combined delayed Smart Reset inputs (SR0,SR1) and provides an adjustable reset delay setup time via an external capacitor connected to the SRC pin. TheRSToutput depends also on the VCCmonitoring threshold. STM6505 also provides independent low battery detect (BLD) output controlled by the secondary external input voltage VBAT. VBATis monitored for low voltage and provides an indication on the battery low detect output pin (BLD). VBATthreshold is 1.25 V, fixed, and an external resistor divider is to be used to set the actual battery voltage threshold. VBATthreshold hysteresis is 8 mV typ. (16 mV max.). VBATis voltage monitoring input only, the device is powered only from the VCCpin; VCCmust be ≥ 1.575 V for proper operation of the VBATcomparator. |
| PMIC | 3 | Active | |
STM6513Dual push-button Smart Reset with dual reset outputs and user-selectable setup delay | Supervisors | 3 | Active | The STM6513 has two separate delayed Smart Reset inputs (SR0,SR1) which when taken low simultaneously provide three user-selectable delayed Smart Reset setup time (tSRC) options of 2 s, 6 s and 10 s. These are selected through a three-state TSR input pin: when connected to ground, tSRC= 2 s; when left open, tSRC= 6 s; when connected to VCC, tSRC= 10 s (all the times are minimum). There are two reset outputs, both going active simultaneously after both the Smart Reset inputs were held active for the selected tSRCdelay time. The first reset output, RST1, is active-high, push-pull; the second reset output,RST2, is active-low, open-drain requiring an external pull-up resistor. The duration of the output reset pulses is independently programmable: tREC1is user-programmable (by external capacitor CtREC), tREC2is factory-programmed to 210 ms (typ.), with the option of 360 ms typ. Additionally, the VCCis monitored and if it drops below the selected VRSTthreshold, both the reset outputs go active and remain so while VCCis below the VRSTthreshold, plus the defined duration of the reset pulse tRECon each output. |
| PMIC | 7 | Active | |
| Supervisors | 1 | Active | |
