Renesas Electronics Corporation

The 85222 is a Dual LVCMOS / LVTTL-to- Differential LVHSTL Translator. The 85222 has two single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to LVHSTL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important. For optimum performance, both output pairs need to be terminated, even if one output pair is unused.

The 8523 is a low skew, high performance 1-to-4 Differential-to-HSTL Fanout Buffer. The 8523 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8523 ideal for those applications demanding well defined performance and repeatability.

The 8524 is a low skew, 1-to-22 Differential-to-HSTL Fanout Buffer . The 8524 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The 8524's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.

The ICS85304I-01 is a low-skew, high-performance 1-to-5 differential-to-3.3V LVPECL fanout buffer. The ICS85304I-01 has two selectable clock inputs. The CLKx, nCLKx pairs can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/de-assertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the ICS85304I-01 ideal for those applications demanding well-defined performance and repeatability.

The 8530I-01 is a low skew, 1-to-16 Differential- to-3.3V LVPECL Fanout Buffer. The CLK, nCLK pair can accept most standard differential input levels. The high gain differential amplifier accepts peak-to-peak input voltages as small as 150mV as long as the common mode voltage is within the specified minimum and maximum range. Guaranteed output and part-to-part skew characteristics make the 8530I-01 ideal for those clock distribution applications demanding well defined performance and repeatability.

The 8531-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer and a member of the family of High Performance Clock Solutions from IDT. The 8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output skew and part-to-part skew characteristics make the 8531-01 ideal for high performance workstation and server applications.

The 85314I-11 is a low skew, high performance 1-to-5 Differential-to-2.5V/3.3V LVPECL fanout buffer. The 85314I-11 has two selectable differential clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. The clock enable is internally synchronized to eliminate runt clock pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 85314I-11 ideal for those applications demanding well defined performance and repeatability.

The 85320I is a LVCMOS / LVTTL-to-Differential 3.3V, 2.5V LVPECL translator. The 85320I has a single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels and translates them to 3.3V or 2.5V LVPECL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.

The 85322I is a Dual LVCMOS / LVTTL-to- Differential 2.5V / 3.3V LVPECL translator. The 85322I has selectable single ended clock inputs. The single ended clock input accepts LVCMOS or LVTTL input levels and translate them to 2.5V / 3.3V LVPECL levels. The small outline 8-pin SOIC package makes this device ideal for applications where space, high performance and low power are important.