810252DI-02VCXO Jitter Attenuator & FemtoClock® Multiplier | Clock/Timing | 1 | Obsolete | The 810252DI-02 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock® frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins. The multiplication ratios are optimized to support most common clock rates used in PDH, SONET and Ethernet applications. The VCXO requires the use of an external, inexpensive pullable crystal. The VCXO uses external passive loop filter components which allows configuration of the PLL loop bandwidth and damping characteristics. The device is packaged in a space-saving 32-VFQFN package and supports industrial temperature range. |
813076IFrequency Generator/Jitter Attenuation Device For Wireless Infrastructure Applications | Clock/Timing | 1 | Obsolete | The 813076I is a member of the family of high performance clock solutions from IDT. The 813076I a PLL based synchronous clock solution that is optimized for wireless infrastructure equipment where frequency translation and jitter attenuation is needed.
The device contains two internal PLL stages that are cascaded in series. The first PLL stage attenuates the reference clock jitter by using an internal or external VCXO circuit. The internal VCXO requires the connection of an external inexpensive pullable crystal (XTAL) to the 813076I. This first PLL stage (VCXO PLL) uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application. The output of the first stage VCXO PLL is a stable and jitter-tolerant reference input for the second PLL stage of 30.72MHz. The second PLL stage provides frequency translation by multiplying the output of the first stage up to 614.4MHz. The low phase noise characteristics of the clock signal is maintained by the internal FemtoClock® PLL, which requires no external components or configuration. Two independently configurable frequency dividers translate the 491.52MHz or 614.4MHz internal VCO signal to the desired output frequencies. All frequency translation ratios are set by device configuration pins. Alternative to the clock frequency multiplication functionality, the 813076I can work as a VCXO. Enabling the VCXO mode allows the output frequency of 614.4MHz/N or 491.52MHz/N to be pulled by the input voltage of the VC pin. |
| Clock Generators, PLLs, Frequency Synthesizers | 1 | Obsolete | |
| Clock/Timing | 3 | Active | |
| CODECs | 4 | Active | |
| Interface | 2 | Obsolete | |
| Integrated Circuits (ICs) | 1 | Obsolete | |
82C84ACMOS Clock Generator Driver | Integrated Circuits (ICs) | 1 | Obsolete | The Intersil 82C84A is a high performance CMOS Clock Generatordriver which is designed to service the requirements of both CMOS and NMOS microprocessors such as the 80C86, 80C88, 8086 and the 8088. The chip contains a crystal controlled oscillator, a divide-bythree counter and complete "Ready" synchronization and reset logic. Static CMOS circuit design permits operation with an external frequency source from DC to 25MHz. Crystal controlled operation to 25MHz is guaranteed with the use of a parallel, fundamental mode crystal and two small load capacitors. All inputs (except X1 and RES) are TTL compatible over temperature and voltage ranges. Power consumption is a fraction of that of the equivalent bipolar circuits. This speed-power characteristic of CMOS permits the designer to custom tailor his system design with respect to power and/or speed requirements. |
| Integrated Circuits (ICs) | 1 | Obsolete | The Intersil 82C89 Bus Arbiter is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). This circuit, along with the 82C88 bus controller, provides full bus arbitration and control for multi-processor systems. The 82C89 is typically used in medium to large 80C86 or 80C88 systems where access to the bus by several processors must be coordinated. The 82C89 also provides high output current and capacitive drive to eliminate the need for additional bus buffering. Static CMOS circuit design insures low operating power. The advanced Intersil SAJI CMOS process results in performance equal to or greater than existing equivalent products at a significant power savings. |
| Evaluation Boards | 1 | Active | |
