Renesas Electronics Corporation

The 5V49EE901 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V49EE901 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of six 8-bit output dividers. Each output bank can be configured to support LVTTL, LVPECL, LVDS or HCSL logic levels. Out0 (Output 0) supports 3.3V single-ended output only. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable.

The 5V49EE902 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V49EE902 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of six 8-bit output dividers. Each output bank can be configured to support LVTTL, LVPECL, LVDS or HCSL logic levels. Out0 (Output 0) supports 3.3V single-ended output only. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable.

The 5V49EE903 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V49EE903 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of six 8-bit output dividers. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable.

The 5V49EE904 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V49EE904 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of six 8-bit output dividers. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disable function is programmable.

The 5V925BI is a high-performance, low skew, low jitter phase-locked loop (PLL) clock driver. It provides precise phase and frequency alignment of its clock outputs to an externally applied clock input or internal crystal oscillator. The 5V925BI has been specially designed to interface with Gigabit Ethernet and Fast Ethernet applications by providing a 125MHz clock from 25MHz input. It can also be programmed to provide output frequencies ranging from 3.125MHz to 160MHz with input frequencies ranging from 3.125MHz to 80MHz.

The IDT5V9885T is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, andnetworking applications. There are three internal PLLs, each individually programmable, allowing for three unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. A glitchless automatic or manual switchover function allows any one of theredundant clocks to be selected during normal operation.The IDT5V9885T can be programmed through the use of the I2C or JTAG interfaces. The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in-system programmable. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. JTAG boundary scan is also implemented.Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback divider. This allows the user to generate three unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and fractional divides are allowed on two of the PLLs.There are 10-bit post dividers on five of the six output banks. Two of the six output banks are configurable to be LVTTL, LVPECL, or LVDS. Theother four output banks are LVTTL. The outputs are connected to the PLLs via the switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output's slew rate and enable/disablefunction can be programmed.

The 5V9910A is a high fanout phase locked-loop clock driver intended for high performance computing and data-communications applications. It has eight zero delay LVTTL outputs. When the GND/sOE pin is held low, all the outputs are synchronously enabled. However, if GND/sOE is held high, all the outputs except Q2 and Q3 are synchronously disabled. Furthermore, when the VCCQ/PE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When VCCQ/ PE is held low, all the outputs are synchronized with the negative edge of REF. The FB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.