Renesas Electronics Corporation

The IDT9112-16 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz.

The IDT9112-27 is a high performance, low skew, low jitterPCI / PCI-X clock driver. It is designed to distribute highspeed signals in PCI / PCI-X applications operating atspeeds from 0 to 140 MHz.

The IDT91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz.IDT91305 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer.The IDT91305 comes in an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition.

The 9161A-01 is a fully programmable graphics clock generator. It can generate user-specified clock frequencies using an externally generated input reference or a single crystal. The output frequency is programmed by entering a 24-bit digital word through the serial port. Two fully user-programmable phaselocked loops are offered in a single package. One PLL is designed to drive the memory clock, while the second drives the video clock. The outputs may be changed on-the-fly to any desired frequency between 390 kHz and 120 MHz. The 9161A-01 is ideally suited for any design where multiple or varying frequencies are required. This part is ideal for graphics applications. It generates low jitter, high speed pixel clocks. It can be used to replace multiple, expensive high speed crystal oscillators. The flexibility of the device allows it to generate non-standard graphics clocks. The 9161A-01 is also ideal in disk drives. It can generate zone clocks for constant density recording schemes. The low profile, 16-pin SOIC or PDIP package and low jitter outputs are especially attractive in board space critical disk drives.

Low EMI, Spread Modulating, Clock Generator

LOW EMI, SPREAD MODULATING, CLOCK GENERATOR

The IDT9173B provide the analog PLL circuit blocks to implement a frequency multiplier. Because the device is configured to use an external divider in the PLL clock feedback path, a large divider can be used to result in a large frequency multiplication ratio. This is useful when using a low frequency input clock to generate a high frequency output clock. The IDT9173B contains a phase detector, charge pump, loop filter, and voltage-controlled oscillator (VCO). The IDT674-01 can be used as the external feedback divider.

The 9212-13 is a High-speed clock generator providing up to 600 MHz differential clock source for direct Rambus™ memory system. It includes DDLL (Distributed Delay locked loop) and phase detection mechanism to synchronize the direct Rambus™ channel clock to an external system clock. 9212-13 provides a solution for a broad range of Direct Rambus memory applications. The device works in conjunction with the 9250-09. The 9212-13 power management support system turns "off" the Rambus™ channel clock to minimize power consumption for mobile and other power–sensitive applications. In "clock off" mode the device remains "on" while the output is disabled, allowing fast transitions between clock-off and clock–on states. In "power down" mode it completely powers down for minimum power dissipation. The 9212-13 meets the requirements for input frequency tracking when the input frequency clock is using Spread Spectrum clocking and also the optimum bandwidth is maintained while attenuating the jitter of the reference signal.

The 9214 clock generator provides the necessary clock signals to support the Rambus XDRTM memory subsystem and Redwood logic interface. The clock source is a reference clock that may or may not be modulated for spread spectrum. The 9214 provides 4 differential clock pairs in a space saving 28-pin TSSOP package and provides an off-the-shelf high-performance interface solution. Figure 1 shows the major components of the 9214 XDR Clock Generator. These include the a PLL, a Bypass Multiplexer and four differential output buffers. The outputs can be disabled by a logic low on the OE pin. An output is enabled by the combination of the OE pin being high, and 1 in its SMBus Output control register bit. The PLL receives a reference clock, CLK_INT/C and outputs a clock signal at a frequency equal to the input frequency times a multiplier. Table 2 shows the multipliers selectable via the SMBus interface. This clock signal is then fed to the differential output buffers to drive the enabled clocks. Disabled outputs are set to Hi-Z. The Bypass mode routes the input clock, CLK_INT/C, directly to the differential output buffers, bypassing the PLL. Up to four 9214 devices can be cascaded on the same SMBus. Table 3 shows the SMBus addressing and control for the four devices.