O
ON Semiconductor
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Part | Spec A | Spec B | Spec C | Spec D | Description |
|---|---|---|---|---|---|
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Part | Spec A | Spec B | Spec C | Spec D | Description |
|---|---|---|---|---|---|
| Part | Category | Description |
|---|---|---|
ON Semiconductor | Integrated Circuits (ICs) | SELF-PROTECTED N-CHANNEL POWER MOSFET/ REEL |
ON Semiconductor 74AC32PCObsolete | Integrated Circuits (ICs) | IC GATE OR 4CH 2-INP 14MDIP |
ON Semiconductor | Discrete Semiconductor Products | IGBT, 360V, 27A, 1.32V, 320MJ, TO-262<BR>ECOSPARK® I, N-CHANNEL IGNITION |
ON Semiconductor FAN1655MTFXObsolete | Integrated Circuits (ICs) | IC REG CTRLR DDR 1OUT 16TSSOP |
ON Semiconductor FIN1027MObsolete | Integrated Circuits (ICs) | LVDS DRIVER, LVDS DIFFERENTIAL DRIVER, -40 °C, 85 °C, 3 V, 3.6 V, SOIC |
ON Semiconductor | Integrated Circuits (ICs) | PIPELINE REGISTER, 8-BIT PQCC28 |
ON Semiconductor SLV4HC4053ADWRGObsolete | Integrated Circuits (ICs) | LDO REGULATOR, ULTRA-LOW NOISE, |
ON Semiconductor | Isolators | OPTOCOUPLER, DIP, 6 PINS, 5 KV, NON ZERO CROSSING, 800 V, FOD4218 SERIES |
ON Semiconductor NVMFD5483NLT1GObsolete | Discrete Semiconductor Products | DUAL N-CHANNEL POWER MOSFET 60V, 24A, 36MΩ |
ON Semiconductor | Discrete Semiconductor Products | BIP NPN 8A 50V |
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Integrated Circuits (ICs) | 1 | Obsolete | ||
| Integrated Circuits (ICs) | 1 | Obsolete | ||
| Integrated Circuits (ICs) | 1 | Obsolete | ||
NB3F8L3010CClock / Data Fanout Buffer, 3:1:10 Differential, LVCMOS, 3.3 V / 2.5 V / 1.8 V / 1.5 V | Clock/Timing | 2 | Active | The NB3F8L3010C is a 3:1:10 Clock or Data fanout buffer operating on a 3.3 V or 2.5 V Core VDD and a flexible 3.3 V or 2.5 V or 1.8 V or 1.5 V VDDO supply which must be equal or less than VDD. |
| Evaluation Boards | 1 | Active | ||
| Clock Generators, PLLs, Frequency Synthesizers | 1 | Obsolete | ||
NB3H83905CClock Fanout Buffer, Crystal Input, 1:6 LVTTL/LVCMOS, with Output Enable | Clock/Timing | 3 | Active | The NB3H83905C is a 1.8 V, 2.5 V Crystal input to 1:6 LVTTL/LVCMOS fanout buffer with outputs powered by a flexible 1.8 V, 2.5 V, or 3.3 V supply (VDD must be greater than VDDO). The core accepts a fundamental Parallel Resonant crystal from 3 MHz to 40 MHz or a Single Ended LVCMOS Clock from 3 MHz to 100 MHz. Core supply must be equal or greater voltage than the output supply. |
| Integrated Circuits (ICs) | 1 | Obsolete | ||
NB3L202K2.5V, 3.3V Differential 1:2 HCSL Fanout Buffer | Evaluation and Demonstration Boards and Kits | 2 | Active | The NB3L202K is a differential 1:2 Clock fanout buffer withHigh−speed Current Steering Logic (HCSL) outputs. Inputs candirectly accept differential LVPECL, LVDS, and HCSL signals.Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels areaccepted with a proper external Vth reference supply per Figures 4and 6. The input signal will be translated to HCSL and provides twoidentical copies operating up to 350 MHz.The NB3L202K is optimized for ultra−low phase noise, propagationdelay variation and low output–to–output skew, and is DB200Hcompliant. As such, system designers can take advantage of theNB3L202K’s performance to distribute low skew clocks across thebackplane or the motherboard making it ideal for Clock and Datadistribution applications such as PCI Express, FBDIMM, Networking,Mobile Computing, Gigabit Ethernet, etc.Output drive current is set by connecting a 475 resistor fromIREF (Pin 10) to GND per Figure 11. Outputs can also interface toLVDS receivers when terminated per Figure 12. |
NB3L208K2.5V, 3.3V Differential 1:8 HCSL Fanout Buffer | Clock Buffers, Drivers | 1 | Active | The NB3L208K is a differential 1:8 Clock fanout buffer withHigh−speed Current Steering Logic (HCSL) outputs. Inputs candirectly accept differential LVPECL, LVDS, and HCSL signals.Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels areaccepted with a proper external Vth reference supply per Figures 4and 6. The input signal will be translated to HCSL and provides eightidentical copies operating up to 350 MHz.The NB3L208K is optimized for ultra−low phase noise, propagationdelay variation and low output–to–output skew, and is DB800Hcompliant. As such, system designers can take advantage of theNB3L208K’s performance to distribute low skew clocks across thebackplane or the motherboard making it ideal for Clock and Datadistribution applications such as PCI Express, FBDIMM, Networking,Mobile Computing, Gigabit Ethernet, etc.Output drive current is set by connecting a 475 resistor fromIREF (Pin 27) to GND per Figure 11. Outputs can also interface toLVDS receivers when terminated per Figure 12. |