ON Semiconductor

The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBBoutput should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The VBBoutput is designed to act as the switching reference for the input of the EL15 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input.The common enable (ENbar) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.The 100 series contains temperature compensation.

The MC10EL/100EL16 is a differential receiver. The device is functionally equivalent to the E116 device with higher performance capabilities. With output transition times significantly faster than the E116 the EL16 is ideally suited for interfacing with high frequency sources.The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 F capacitor and limit current sourcing or sinking to 0.5mA. When not used, VBBshould be left open.Under open input conditions (pulled to VEE) internal input clamps will force the Q output LOW.The 100 Series contains temperature compensation.

The MC100EL1648 requires an external parallel tank circuit consisting of the inductor (L) and capacitor (C). A varactor diode may be incorporated into the tank circuit to provide a voltage variable input for the oscillator (VCO). This device may also be used in many other applications requiring a fixed frequency clock. The MC100EL1648 is ideal in applications requiring a local oscillator. Systems include electronic test equipment and digital high-speed telecommunications.The MC100EL1648 is based on the VCOcircuit topology of the MC1648. The MC100EL1648 uses advanced bipolar process technology which results in a design which can operate at an extended frequency range.The ECL output circuitry of the MC100EL1648 is not a traditional open emitter output structure and instead has an on-chip termination resistor with a nominal value of 510 ohms. This facilitates direct ac-coupling of the output signal into a transmission line. Because of this output configuration, an external pull-down resistor is not required to provide the output with a dc current path. This output is intended to drive one ECL load. If the user needs to fanout the signal, an ECL buffer such as the MC10EL16 Line Receiver/Driver should be usedNOTE: The MC100EL1648 is NOT useable as a crystal oscillator.

The MC10EL/100EL31 is a D flip-flop with set and reset. The device is functionally equivalent to the E131 device with higher performance capabilities. With propagation delays and output transition times significantly faster than the E131 the EL31 is ideally suited for those applications which require the ultimate in AC performance.Both set and reset inputs are asynchronous, level triggered signals. Data enters the master portion of the flip-flop when clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.The 100 Series contains temperature compensation.

The MC10EL/100EL32 is an integrateddivide by 2 divider. The differential clock inputs and the VBBallow a differential, single-ended or AC coupled interface to the device. If used, the VBBoutput should be bypassed to ground with a 0.01 F capacitor. Also note that the VBBis designed to be used as an input bias on the EL32 only, the VBBoutput has limited current sink and source capability.The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flop will attain a random state; the reset allows for the synchronization of multiple EL32's in a system.The 100 Series contains temperature compensation.

The MC100EL38 is a low skew divide by 2, divide by 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal.The VBBpin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBBas a switching reference voltage. VBBmay also rebias AC coupled inputs. When used, decouple VBBand VCCvia a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBBshould be left open.The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.The Phase_Out output will go HIGH for one clock cycle whenever the divide by 2 and the divide by 4/6 outputs are both transitioning from a LOW to a HIGH. This output allows for clock synchronization within the system.Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EL38s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EL38, the MR pin need not be exercised as the internal divider design ensures synchronization bet