| Integrated Circuits (ICs) | 1 | Active | The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. |
| Integrated Circuits (ICs) | 1 | Active | The 74AHC30-Q100; 74AHCT30-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. |
| Gates and Inverters | 1 | Active | The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. |
| Integrated Circuits (ICs) | 1 | Active | The 74AHC30; 74AHCT30 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. |
| Integrated Circuits (ICs) | 1 | Active | The 74AHC30-Q100; 74AHCT30-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. |
| Gates and Inverters | 6 | Active | The 74AHC32-Q100; 74AHCT32-Q100 is a quad 2-input OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Gates and Inverters | 1 | Active | The 74AHC32; 74AHCT32 is a quad 2-input OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 1 | Active | The 74AHC32-Q100; 74AHCT32-Q100 is a quad 2-input OR gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
74AHC373Octal D-type transparant latch; 3-state | Logic | 4 | Active | The 74AHC373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the latches. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
74AHC374Octal D-type flip-flop; positive edge-trigger; 3-state | Integrated Circuits (ICs) | 5 | Active | The 74AHC374-Q100; 74AHCT374-Q100 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the flip-flops. Inputs are overvoltage tolerant. The 74AHCT374-Q100 device features TTL compatible inputs that are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
