| Buffers, Drivers, Receivers, Transceivers | 1 | Active | The 74AHC244-Q100; 74AHCT244-Q100 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OEand 2OE), each controlling four of the 3-state outputs. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 1 | Active | The 74AHC244; 74AHCT244 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OEand 2OE), each controlling four of the 3-state outputs. A HIGH on nOEcauses the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Buffers, Drivers, Receivers, Transceivers | 8 | Active | The 74AHC245-Q100; 74AHCT245-Q100 is an 8-bit transceiver with 3-state outputs. The device features an output enable (OE) and send/receive (DIR) for direction control. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Integrated Circuits (ICs) | 1 | Active | The 74AHC257-Q100 is a quad 2-input multiplexer with 3-state outputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 1 | Active | The 74AHC257; 74AHCT257 is a quad 2-input multiplexer with 3-state outputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
74AHC273Octal D-type flip-flop with reset; positive-edge trigger | Integrated Circuits (ICs) | 5 | Active | The 74AHC273-Q100; 74AHCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW onMRforces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
74AHC273BQOctal D-type flip-flop with reset; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74AHC273; 74AHCT273 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW onMRforces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
74AHC273D-Q100Octal D-type flip-flop with reset; positive-edge trigger | Flip Flops | 1 | Active | The 74AHC273-Q100; 74AHCT273-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and master reset (MR) inputs. The outputs Qn will assume the state of their corresponding D inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A LOW onMRforces the outputs LOW independently of clock and data inputs. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
| Logic | 4 | Active | The 74AHC2G00-Q100; 74AHCT2G00-Q100 are high-speed Si-gate CMOS devices. They provide two 2-input NAND gates. |
| Logic | 2 | Active | The 74AHC2G08-Q100; 74AHCT2G08-Q100 is a dual 2-input AND gate. Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. |
