74LVC1G80GMSingle D-type flip-flop; positive-edge trigger | Flip Flops | 1 | Active | The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at theQoutput. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
74LVC1G80GSSingle D-type flip-flop; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at theQoutput. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
74LVC1G80GVSingle D-type flip-flop; positive-edge trigger | Flip Flops | 1 | Active | The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at theQoutput. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
74LVC1G80GWSingle D-type flip-flop; positive-edge trigger | Logic | 1 | Active | The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at theQoutput. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
| Flip Flops | 1 | Active | The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at theQoutput. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
74LVC1G80GZSingle D-type flip-flop; positive-edge trigger | Logic | 1 | Active | The 74LVC1G80 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at theQoutput. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
| Integrated Circuits (ICs) | 1 | Active | The 74LVC1G80-Q100 is a single positive-edge triggered D-type flip-flop. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and its complement will appear at theQoutput. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
| Logic | 5 | Active | The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. |
| Gates and Inverters | 1 | Active | The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. |
| Integrated Circuits (ICs) | 1 | Active | The 74LVC1G86 provides the 2-input EXCLUSIVE-OR function. |
