| Integrated Circuits (ICs) | 1 | Active | The 74LV541AT is an 8-bit buffer/line driver with 3-state outputs and TTL inputs. The device features two output enables (OE1 andOE2). A HIGH onOEn causes the associated outputs to assume a high-impedance OFF-state. |
| Integrated Circuits (ICs) | 1 | Obsolete | |
74LV5958-bit serial-in/serial-out or parallel-out shift register; 3-state | Integrated Circuits (ICs) | 5 | Active | The 74LV595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous resetMRinput. A LOW onMRwill reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
| Gates and Inverters | 1 | Active | |
| Gates and Inverters | 1 | Active | The 74LV7032A-Q100 is a quad 2-input OR function with Schmitt-trigger inputs, capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. |
| Logic | 1 | Active | |
74LV74D-Q100Dual D-type flip-flop with set and reset; positive-edge trigger | Logic | 1 | Active | The 74LV74-Q100 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
74LV74PWDual D-type flip-flop with set and reset; positive-edge trigger | Integrated Circuits (ICs) | 1 | Active | The 74LV74 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
74LV74PW-Q100Dual D-type flip-flop with set and reset; positive-edge trigger | Logic | 1 | Active | The 74LV74-Q100 is a dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQoutputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the nQ output. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
| Integrated Circuits (ICs) | 6 | Active | The 74LVC00A is a quad 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. |
