74LV4053BQTriple single-pole double-throw analog switch | Interface | 1 | Active | The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use in 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (Y0 and Y1) and a common input/output (Z). A digital enable input (E) is common to all switches. WhenEis HIGH, the switches are turned off. |
| Analog Switches, Multiplexers, Demultiplexers | 1 | Active | The 74LV4053-Q100 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053-Q100 and 74HCT4053-Q100. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH onEcauses all switches into the high-impedance OFF-state, independent of Sn. |
74LV4053DTriple single-pole double-throw analog switch | Interface | 1 | Active | The 74LV4053 is a triple single-pole double-throw (SPDT) analog switch, suitable for use in 2:1 multiplexer/demultiplexer applications. Each switch features a digital select input (Sn), two independent inputs/outputs (Y0 and Y1) and a common input/output (Z). A digital enable input (E) is common to all switches. WhenEis HIGH, the switches are turned off. |
| Analog Switches, Multiplexers, Demultiplexers | 1 | Active | The 74LV4053-Q100 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053-Q100 and 74HCT4053-Q100. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH onEcauses all switches into the high-impedance OFF-state, independent of Sn. |
| Interface | 1 | Active | The 74LV4053-Q100 is a triple single-pole double-throw (SPDT) analog switch, suitable for use as an analog or digital multiplexer/demultiplexer. It is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4053-Q100 and 74HCT4053-Q100. Each switch has a digital select input (Sn), two independent inputs/outputs (nY0 and nY1) and a common input/output (nZ). All three switches share an enable input (E). A HIGH onEcauses all switches into the high-impedance OFF-state, independent of Sn. |
74LV406014-stage binary ripple counter with oscillator | Counters, Dividers | 5 | Active | The 74LV4060-Q100 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTCand CTC), ten buffered parallel outputs (Q3to Q9and Q11to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTCand CTC) floating. The counter advances on the HIGH-to-LOW transition of RS. A HIGH level on MR clears all counter stages and forces all outputs LOW, independent of the other input conditions. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
| Counters, Dividers | 1 | Active | The 74LV4060-Q100 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTCand CTC), ten buffered parallel outputs (Q3to Q9and Q11to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTCand CTC) floating. The counter advances on the HIGH-to-LOW transition of RS. A HIGH level on MR clears all counter stages and forces all outputs LOW, independent of the other input conditions. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
| Interface | 5 | Active | The 74LV4066 is a quad single pole, single throw analog switch. Each switch features two input/output terminals (nY and nZ) and an active HIGH enable input (nE). When nE is LOW, the analog switch is turned off. Digital inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
74LV40948-stage shift-and-store bus register | Integrated Circuits (ICs) | 6 | Active | The 74LV4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC. |
| Integrated Circuits (ICs) | 1 | Active | The 74LV541A is an 8-bit buffer/line driver with 3-state outputs. The device features two output enables (OE1 andOE2). A HIGH onOEn causes the associated outputs to assume a high-impedance OFF-state. |
