74HC5958-bit serial-in, serial or parallel-out shift register with output latches; 3-state | Integrated Circuits (ICs) | 6 | Active | The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous resetMRinput. A LOW onMRwill reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC595BZ8-bit serial-in, serial or parallel-out shift register with output latches; 3-state | Integrated Circuits (ICs) | 1 | Active | The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous resetMRinput. A LOW onMRwill reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC595D-Q1008-bit serial-in, serial or parallel-out shift register with output latches; 3-state | Shift Registers | 1 | Active | The 74HC595-Q100; 74HCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous resetMRinput. A LOW onMRwill reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC5978-bit shift register with input flip-flops | Integrated Circuits (ICs) | 5 | Active | The 74HC597-Q100; 74HCT597-Q100 is an 8-bit shift register with input flip-flops. It consists of an 8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and the shift register have positive edge-triggered clocks. The shift register also has direct load (from storage) and clear inputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Logic | 2 | Obsolete | |
| Logic | 3 | Active | The 74HC688 is an 8-bit magnitude comparator. It performs comparisons of two 8-bit binary or BCD words. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC7014Hex non-inverting precision Schmitt-trigger | Logic | 3 | Active | The 74HC7014-Q100 is a hex buffer with precision Schmitt-trigger inputs. The precisely defined trigger levels are lying in a window between 0.55 × VCCand 0.65 × VCC. It makes the circuit suitable to operate in a highly noisy environment. Input shorts are allowed to -1.5 V and +16 V without disturbing other channels. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals. |
74HC73Dual JK flip-flop with reset; negative-edge trigger | Integrated Circuits (ICs) | 5 | Active | The 74HC73-Q100 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQoutputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQoutput HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC73DDual JK flip-flop with reset; negative-edge trigger | Logic | 1 | Active | The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQoutputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQoutput HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC74Dual D-type flip-flop with set and reset; positive edge-trigger | Flip Flops | 7 | Active | The 74HC74-Q100; 74HCT74-Q100 are dual positive edge triggered D-type flip-flop with individual data (nD), clock (nCP), set (nSD) and reset (nRD) inputs, and complementary nQ and nQoutputs. Data at the nD-input, that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition, will be stored in the flip-flop and appear at the nQ output. The Schmitt-trigger action in the clock input, makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
