74HC367Hex buffer/line driver; 3-state | Logic | 5 | Active | The 74HC367; 74HCT367 is a hex buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOEcauses the outputs to assume a high impedance OFF-state. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Integrated Circuits (ICs) | 1 | Obsolete | |
74HC368DHex buffer/line driver; 3-state; inverting | Logic | 1 | Active | The 74HC368; 74HCT368 is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOEcauses the outputs to assume a high impedance OFF-state. Inputs include clamp diodes enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC368PWHex buffer/line driver; 3-state; inverting | Integrated Circuits (ICs) | 1 | Active | The 74HC368; 74HCT368 is a hex inverting buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOEcauses the outputs to assume a high impedance OFF-state. Inputs include clamp diodes enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC373Octal D-type transparent latch; 3-state | Latches | 7 | Active | The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC373PWOctal D-type transparent latch; 3-state | Latches | 1 | Active | The 74HC373; 74HCT373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
| Integrated Circuits (ICs) | 1 | Active | The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC374Octal D-type flip-flop; positive edge-trigger; 3-state | Flip Flops | 3 | Active | The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the flip-flops. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC374DOctal D-type flip-flop; positive edge-trigger; 3-state | Logic | 1 | Active | The 74HC374; 74HCT374 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH onOEcauses the outputs to assume a high-impedance OFF-state. Operation of theOEinput does not affect the state of the flip-flops. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
74HC377Octal D-type flip-flop with data enable; positive-edge trigger | Logic | 7 | Active | The 74HC377-Q100; 74HCT377-Q100 is an octal positive-edge triggered D-type flip-flop. The device features clock (CP) and data enable (E) inputs. WhenEis LOW, the outputs Qn assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. InputEmust be stable one set-up time prior to the LOW-to-HIGH transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. |
