Nexperia USA Inc.

The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications.

The 74HC165-Q100; 74HCT165-Q100 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications.

The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications.

The 74HC165-Q100; 74HCT165-Q100 are 8-bit serial or parallel-in/serial-out shift registers. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary serial outputs (Q7 andQ7). When the parallel load input (PL) is LOW the data from D0 to D7 is loaded into the shift register asynchronously. WhenPLis HIGH data enters the register serially at DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of the CP input. A HIGH onCEwill disable the CP input. Inputs are overvoltage tolerant to 15 V. This enables the device to be used in HIGH-to-LOW level shifting applications.

The 74HC166-Q100; 74HCT166-Q100 is an 8-bit serial or parallel-in/serial-out shift register. The device features a serial data input (DS), eight parallel data inputs (D0 to D7) and a serial output (Q7). When the parallel enable input (PE) is LOW, the data from D0 to D7 is loaded into the shift register on the next LOW-to-HIGH transition of the clock input (CP). WhenPEis HIGH, data enters the register serially at DS with each LOW-to-HIGH transition of CP. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of CP. A HIGH onCEdisables the CP input. Inputs include clamp diodes which enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74HC173-Q100; 74HCT173-Q100 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1,E2) and two output enable (OE1,OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1,E2) and two output enable (OE1,OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW onMRcauses the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.