Microchip Technology

The ZL30643 is a feature-rich line card solution with up to six independent DPLLs and five extremely low output jitter synthesizers. This solution is ideal for line card timing applications such as routers, switches, optical transparent network and 4G/5G wireless base stations. We also have ZL3063x as SyncE Timing Card Synchronizer, such as [**ZL30634A**](https://www.microchip.com/wwwproducts/en/ZL30634A), or ZL3073x as SyncE&1588 Timing Card Synchronizer, such as [**ZL30735A**](https://www.microchip.com/en-us/product/ZL30735A), to form full SyncE&IEEE1588 Timing solution.

The ZL30644 is a feature-rich line card solution with up to seven independent DPLLs and five extremely low output jitter synthesizers. This solution is ideal for line card timing applications such as routers, switches, optical transparent network and 4G/5G wireless base stations. We also have ZL3063x as SyncE Timing Card Synchronizer, such as [**ZL30634A**](https://www.microchip.com/wwwproducts/en/ZL30634A), or ZL3073x as SyncE&1588 Timing Card Synchronizer, such as [**ZL30735A**](https://www.microchip.com/en-us/product/ZL30735A), to form full SyncE&IEEE1588 Timing solution.

The ZL30644A is a feature-rich line card solution with up to seven independent DPLLs, five extremely low output jitter synthesizers and embedded time-of-day (eToD) features. The eToD features include a 3-wire MiToDBasic output interface and a 1-wire MiToDSync input/output interface.This solution is ideal for line card timing applications such as routers, switches, optical transparent network and 4G/5G wireless base stations. We also have ZL3063x as SyncE Timing Card Synchronizer, such as [**ZL30634A**](https://www.microchip.com/en-us/product/zl30634a), or ZL3073x as SyncE&1588 Timing Card Synchronizer, such as [**ZL30735A**](https://www.microchip.com/en-us/product/zl30735a), to form full SyncE&IEEE1588 Timing solution.

The ZL30671 offers one channel of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, this device offers new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make this device ideal for use in chassis based systems with active and redundant timing cards as well as in single board ("pizza box") applications where a timing device needs to have features of both a timing and a line card PLL. Log in to your [MyMicrochip](https://login.microchip.com/ssologin/Account/Login?ReturnUrl=%2Fssologin%2Fconnect%2Fauthorize%2Fcallback%3Fclient_id%3DAuthenticatedUserapi%26redirect_uri%3Dhttps%253A%252F%252Fwww.microchip.com%252Fmymicrochip%252F%2523%252Fcallback%26response_type%3Dcode%26scope%3Dopenid%2520profile%2520AuthenticatedUserapi%26state%3Dd0743a67132a4f7cabf87766498ef7a5%26code_challenge%3D7VwT2FZLyz0rJZj7k5oY1o1voVEo9eQaaVmfjNzodVQ%26code_challenge_method%3DS256%26response_mode%3Dquery) account (with SDE enabled) and request for data sheet and the following application notes. AN3467 Crystals and Oscillators for Next Generation Timing Solutions ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices ZLAN-656 Redwood PSNR ZLAN-664 Board Design Recommendations for Redwood ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package ZLAN-724 Phase Measurement Compensation for Redwood ZLAN-728 Indirect Read and Write Procedure

The ZL30672 offers 2 channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, this device offers new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make this device ideal for use in chassis based systems with active and redundant timing cards as well as in single board ("pizza box") applications where a timing device needs to have features of both a timing and a line card PLL. Log in to your [MyMicrochip](https://login.microchip.com/ssologin/Account/Login?ReturnUrl=%2Fssologin%2Fconnect%2Fauthorize%2Fcallback%3Fclient_id%3DAuthenticatedUserapi%26redirect_uri%3Dhttps%253A%252F%252Fwww.microchip.com%252Fmymicrochip%252F%2523%252Fcallback%26response_type%3Dcode%26scope%3Dopenid%2520profile%2520AuthenticatedUserapi%26state%3Dd0743a67132a4f7cabf87766498ef7a5%26code_challenge%3D7VwT2FZLyz0rJZj7k5oY1o1voVEo9eQaaVmfjNzodVQ%26code_challenge_method%3DS256%26response_mode%3Dquery) account (with SDE enabled) and request for data sheet and the following application notes. AN3467 Crystals and Oscillators for Next Generation Timing Solutions ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices ZLAN-656 Redwood PSNR ZLAN-664 Board Design Recommendations for Redwood ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package ZLAN-724 Phase Measurement Compensation for Redwood ZLAN-728 Indirect Read and Write Procedure

The ZL30673 offers 3 channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, this device offers new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make this device ideal for use in chassis based systems with active and redundant timing cards as well as in single board ("pizza box") applications where a timing device needs to have features of both a timing and a line card PLL. Log in to your [MyMicrochip](https://login.microchip.com/ssologin/Account/Login?ReturnUrl=%2Fssologin%2Fconnect%2Fauthorize%2Fcallback%3Fclient_id%3DAuthenticatedUserapi%26redirect_uri%3Dhttps%253A%252F%252Fwww.microchip.com%252Fmymicrochip%252F%2523%252Fcallback%26response_type%3Dcode%26scope%3Dopenid%2520profile%2520AuthenticatedUserapi%26state%3Dd0743a67132a4f7cabf87766498ef7a5%26code_challenge%3D7VwT2FZLyz0rJZj7k5oY1o1voVEo9eQaaVmfjNzodVQ%26code_challenge_method%3DS256%26response_mode%3Dquery) account (with SDE enabled) and request for data sheet and the following application notes. AN3467 Crystals and Oscillators for Next Generation Timing Solutions ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices ZLAN-656 Redwood PSNR ZLAN-664 Board Design Recommendations for Redwood ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package ZLAN-724 Phase Measurement Compensation for Redwood ZLAN-728 Indirect Read and Write Procedure

The ZL30682 offers two DPLL channel of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by line card PLL. High integration along with ultra-low jitter make these devices ideal for use in frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail. Under the same family, the [ZL3067x](https://www.microchip.com/wwwproducts/en/ZL30673)offer one to three channels of Synchronous Ethernet (SyncE) packet clock synchronization for timing card interface. Also available is [ZL3077x](https://www.microchip.com/wwwproducts/en/ZL30773)that support one to three independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms. Log in to your [MyMicrochip](https://login.microchip.com/ssologin/Account/Login?ReturnUrl=%2Fssologin%2Fconnect%2Fauthorize%2Fcallback%3Fclient_id%3DAuthenticatedUserapi%26redirect_uri%3Dhttps%253A%252F%252Fwww.microchip.com%252Fmymicrochip%252F%2523%252Fcallback%26response_type%3Dcode%26scope%3Dopenid%2520profile%2520AuthenticatedUserapi%26state%3Dd0743a67132a4f7cabf87766498ef7a5%26code_challenge%3D7VwT2FZLyz0rJZj7k5oY1o1voVEo9eQaaVmfjNzodVQ%26code_challenge_method%3DS256%26response_mode%3Dquery) account (with SDE enabled) and request for data sheet and the following application notes. AN3467 Crystals and Oscillators for Next Generation Timing Solutions ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices ZLAN-656 Redwood PSNR ZLAN-664 Board Design Recommendations for Redwood ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package ZLAN-724 Phase Measurement Compensation for Redwood ZLAN-728 Indirect Read and Write Procedure

The ZL30683 offers three DPLL channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by line card PLL. High integration along with ultra-low jitter make these devices ideal for use in frequency translation from backplane clock to frequencies required by PHY devices, jitter filtering, and holdover in case both active and redundant timing cards fail. Under the same family, the [ZL3067x](https://www.microchip.com/wwwproducts/en/ZL30673)offer one to three channels of Synchronous Ethernet (SyncE) packet clock synchronization for timing card interface. Also available is [ZL3077x](https://www.microchip.com/wwwproducts/en/ZL30773)that support one to three independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms. Log in to your [MyMicrochip](https://login.microchip.com/ssologin/Account/Login?ReturnUrl=%2Fssologin%2Fconnect%2Fauthorize%2Fcallback%3Fclient_id%3DAuthenticatedUserapi%26redirect_uri%3Dhttps%253A%252F%252Fwww.microchip.com%252Fmymicrochip%252F%2523%252Fcallback%26response_type%3Dcode%26scope%3Dopenid%2520profile%2520AuthenticatedUserapi%26state%3Dd0743a67132a4f7cabf87766498ef7a5%26code_challenge%3D7VwT2FZLyz0rJZj7k5oY1o1voVEo9eQaaVmfjNzodVQ%26code_challenge_method%3DS256%26response_mode%3Dquery) account (with SDE enabled) and request for data sheet and the following application notes. AN3467 Crystals and Oscillators for Next Generation Timing Solutions ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices ZLAN-656 Redwood PSNR ZLAN-664 Board Design Recommendations for Redwood ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package ZLAN-724 Phase Measurement Compensation for Redwood ZLAN-728 Indirect Read and Write Procedure

The ZL30692 offers two channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make these devices ideal for use in chassis based systems with active and redundant timing cards as well as in single board ("pizza box") applications where a timing device needs to have features of both a timing and a line card PLL. Under the same family, the [ZL3066x](https://www.microchip.com/wwwproducts/en/ZL30663) offer one to three channels of Synchronous Ethernet (SyncE) packet clock synchronization for line card interface. Also available is [ZL3079x](https://www.microchip.com/wwwproducts/en/ZL30793) that support one to three independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms. Log in to your [MyMicrochip](https://login.microchip.com/ssologin/Account/Login?ReturnUrl=%2Fssologin%2Fconnect%2Fauthorize%2Fcallback%3Fclient_id%3DAuthenticatedUserapi%26redirect_uri%3Dhttps%253A%252F%252Fwww.microchip.com%252Fmymicrochip%252F%2523%252Fcallback%26response_type%3Dcode%26scope%3Dopenid%2520profile%2520AuthenticatedUserapi%26state%3Dd0743a67132a4f7cabf87766498ef7a5%26code_challenge%3D7VwT2FZLyz0rJZj7k5oY1o1voVEo9eQaaVmfjNzodVQ%26code_challenge_method%3DS256%26response_mode%3Dquery) account (with SDE enabled) and request for data sheet and the following application notes. AN3467 Crystals and Oscillators for Next Generation Timing Solutions ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices ZLAN-656 Redwood PSNR ZLAN-664 Board Design Recommendations for Redwood ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package ZLAN-724 Phase Measurement Compensation for Redwood ZLAN-728 Indirect Read and Write Procedure

The ZL30693 offers three channels of Synchronous Ethernet (SyncE) packet clock synchronization. Using Microsemi’s miTimePLL timing technology, these devices offer new and improved features for 5G transport and wireless infrastructure equipment. Each device integrates all features required by a timing card PLL and line card PLL. High integration along with ultra-low jitter make these devices ideal for use in chassis based systems with active and redundant timing cards as well as in single board ("pizza box") applications where a timing device needs to have features of both a timing and a line card PLL. Under the same family, the [ZL3066x](https://www.microchip.com/wwwproducts/en/ZL30663) offer one to three channels of Synchronous Ethernet (SyncE) packet clock synchronization for line card interface. Also available is [ZL3079x](https://www.microchip.com/wwwproducts/en/ZL30793) that support one to three independent timing channels of a combined hardware and software platform including IEEE 1588-2008 Precision Time Protocol Stack and Synchronization Algorithms. Log in to your [MyMicrochip](https://login.microchip.com/ssologin/Account/Login?ReturnUrl=%2Fssologin%2Fconnect%2Fauthorize%2Fcallback%3Fclient_id%3DAuthenticatedUserapi%26redirect_uri%3Dhttps%253A%252F%252Fwww.microchip.com%252Fmymicrochip%252F%2523%252Fcallback%26response_type%3Dcode%26scope%3Dopenid%2520profile%2520AuthenticatedUserapi%26state%3Dd0743a67132a4f7cabf87766498ef7a5%26code_challenge%3D7VwT2FZLyz0rJZj7k5oY1o1voVEo9eQaaVmfjNzodVQ%26code_challenge_method%3DS256%26response_mode%3Dquery) account (with SDE enabled) and request for data sheet and the following application notes. AN3467 Crystals and Oscillators for Next Generation Timing Solutions ZLAN-649 ZL3067x Power Supply Decoupling and Layout Practices ZLAN-656 Redwood PSNR ZLAN-664 Board Design Recommendations for Redwood ZLAN-672 Generating JESD204B Clock SYSREF Using Redwood ZLAN-683 Assembly and PCB Layout Guidelines for 80-lead LGA Package ZLAN-724 Phase Measurement Compensation for Redwood ZLAN-728 Indirect Read and Write Procedure