| Integrated Circuits (ICs) | 1 | Active | |
| Clock/Timing | 4 | Active | The SY89871U is a 2.5V/3.3V
LVPECL output precision clock divider capable of accepting a high-speed
differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock
input signal and dividing down the frequency using a programmable divider ratio
to create a frequency locked lower speed version of the input clock (Bank
B).Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock
system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz
auxiliary clock components.
The differential input buffer has a unique internal termination design
that allows access to the termination network through a VT pin. This
feature allows the device to easily interface to different logic standards. A
VREF-AC reference is included for AC-coupled applications.The SY89871U
includes two phase-matched output banks. Bank A (QA) is a frequency-matched
copy of the input. Bank B (QB0, QB1) is a divided down output of the input
frequency. Bank A and Bank B maintain a matched delay independent of the divider
setting. |
| Clock Buffers, Drivers | 3 | Active | This 2.5V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89872U includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank.Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF- AC reference is included for AC-coupled applications.The SY89872U is part of Micrel's high-speed Precision Edge® timing and distribution family. For 3.3V applications, consider the SY89873L. For applications that require an LVPECL output, consider the SY89872U.The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN). Refer to the "Timing Diagram." |
| Clock Buffers, Drivers | 3 | Active | This 3.3V low-skew, low-jitter, precision LVDS output clock divider accepts any high-speed differential clock input (AC- or DC-coupled) CML, LVPECL, HSTL or LVDS and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. The SY89873L includes two output banks. Bank A is an exact copy of the input clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to all AC- or DC-coupled differential logic standards. A VREF-AC reference is included for AC-coupled applications.The SY89873L is part of Micrel's high-speed Precision Edge® timing and distribution family. For 2.5V applications, consider the SY89872U. For applications that require an LVPECL output, consider the SY89871U.The /RESET input asynchronously resets the divider outputs (Bank B). In the pass-through function (Bank A) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N). Refer to the Timing Diagram. |
| Clock Buffers, Drivers | 2 | Active | This low-skew, low-jitter device can accept a high-speed (622MHz or higher) LVTTL, LVCMOS, CML, LVPECL, LVDS or HSTL clock input signal and divide down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input clock. Available divider ratios are 2, 4, 8, and 16, or straight pass-through. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components.
The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /N).Use the SY89874U version, which has a wider input range, to DC-couple low offset differential signals. |
| Clock Buffers, Drivers | 3 | Active | This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through.The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN). |
| Clock Buffers, Drivers | 3 | Active | This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a lower speed version of the input clock. Available divider ratios are 2, 4, 8 and 16, or straight pass-through.The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications.The /RESET input asynchronously resets the divider. In the pass-through function (divide by 1) the /RESET synchronously enables or disables the outputs on the next falling edge of IN (rising edge of /IN). |
SYA75603AEC-Q100 qualified ultra-Low Jitter, 2 Outputs LP-HCSL Buffer | Integrated Circuits (ICs) | 3 | Active | SYA75603 is an advanced 1:2 LP-HCSL fanout buffer designed for automotive high-performance, low-power, small form factor applications.
The SYA75603 operates at frequencies up to 250MHz with ultra-low additive jitter of 6fs (PCIe Gen6).
The device is AEC-Q100 qualified. The SYA75603 is offered in a small 3 mm x 3 mm wettable flank VQFN-16L package. |
SYA75604AEC-Q100 qualified ultra-Low Jitter, 4 Outputs LP-HCSL Buffer | Clock/Timing | 1 | Active | SYA75604 is an advanced 1:4 LP-HCSL fanout buffer designed for automotive high-performance, low-power, small form factor applications.
The SYA75604 operates at frequencies up to 250MHz with ultra-low additive jitter of 6fs (PCIe Gen6).
The device is AEC-Q100 qualified. The SYA75604 is offered in a small 3 mm x 3 mm wettable flank VQFN-16L package. |
SYA75612AEC-Q100 qualified ultra-Low Jitter, 12 Outputs LP-HCSL Buffer | Clock/Timing | 1 | Active | SYA75612 is an advanced 1:12 LP-HCSL fanout buffer designed for automotive high-performance and low-power applications.
The SYA75612 operates at frequencies up to 250MHz with ultra-low additive jitter of 6fs (PCIe Gen6).
The device is AEC-Q100 qualified. The SYA75612 is offered in a small 8 mm x 8 mm wettable flank VQFN-56L package. |
