| Integrated Circuits (ICs) | 2 | Active | The SY88063CL limiting post amplifier is designed for use in fiber-optic receivers for multi-rate applications from 1.0625Gbps to 12.5Gbps.
The SY88063CL contains a high-bandwidth, high-sensitivity input stage with user-programmable, wide-range SD assert/LOS de-assert threshold levels, which enables optimized system reach. Typically, 4dB of electrical hysteresis is provided to minimize LOS or SD chattering caused by noisy input signals. A logic level control pin is provided to enable user selection of an open-collector, TTL-compatible LOS or SD status indication signal with an external 5kΩ to 10kΩ pull-up resistor.
The SY88063CL provides fast SD assert and LOS de-assert times over the entire differential input voltage range of 5mVPP to 1800mVPP.
The SY88063CL input stage also provides a user-selectable digital offset correction (DOC) function to automatically compensate for internal device offsets in the high-speed data path.
The SY88063CL provides integrated 50Ω input and output impedances to optimize the high-speed signal paths and reduce component count. A TTL-compatible JAM input is provided to enable a SQUELCH function by feeding back the LOS or SD signal. The JAM input disables only the post amplifier output.
The SY88063CL operates from a single +3.3V power supply, over temperatures ranging from –40°C to +85°C.
To request the datasheet, please email us at [tcg\_help@microchip.com](mailto:tcg_help@microchip.com?subject=SY88063CL%20Datasheet) |
| Amplifiers | 2 | Active | The SY88073L limiting post amplifier is designed for use in fiber-optic receivers for continuous mode, multi-rate applications from 1Gbps to 12.5Gbps.
The SY88073L contains a high-bandwidth, high-sensitivity input stage with user-programmable, wide-range SD assert/LOS de-assert threshold levels, which enables optimized system reach. Typically, 4dB of electrical hysteresis is provided to minimize LOS or SD chattering caused by noisy input signals. A logic level control pin is provided to enable user selection of an open-collector, TTL-compatible LOS or SD status indication signal with an external 5kΩ to 10kΩ pull-up resistor.
The SY88073L provides faster SD assert and LOS de-assert times (than typical continuous mode devices) over the entire differential input voltage range of 10mVPP to 1800mVPP.
The SY88073L input stage also provides a user-adjustable decision threshold circuit to optimize BER in noisy applications such as WDM, where EDFA and Raman amplifiers contribute uneven noise levels. By applying an external control voltage, the decision threshold can typically be adjusted from 30% to 70% from the nominal 50% threshold when the circuit is disabled.
The SY88073L provides integrated 50Ω input and output impedances to optimize the high-speed signal paths and reduce component count. The post amplifier outputs have user-selectable polarity inversion control to simplify PCB layout. A TTL-compatible JAM input is provided to enable a SQUELCH function by feeding back the LOS or SD signal. The JAM input disables only the post amplifier output.
The SY88073L operates from a single +3.3V power supply, over temperatures ranging from –40°C to +85°C. |
| Integrated Circuits (ICs) | 2 | Active | The SY88083L limiting post amplifier is designed for use in fiber-optic receivers for continuous mode, multi-rate applications from 1Gbps to 12.5Gbps.
The SY88083L contains a high-bandwidth, high-sensitivity input stage with user-programmable, wide-range SD assert/LOS de-assert threshold levels, which enables optimized system reach. Typically, 4dB of electrical hysteresis is provided to minimize LOS or SD chattering caused by noisy input signals. A logic level control pin is provided to enable user selection of an open-collector, TTL-compatible LOS or SD status indication signal with an external 5kΩ to 10kΩ pull-up resistor.
The SY88083L provides faster SD assert and LOS de-assert times than typical continuous mode devices over the entire differential input voltage range of 10mVPP to 1800mVPP.
The SY88083L input stage also provides a user-selectable digital offset correction (DOC) function to automatically compensate for internal device offsets in the high-speed data path.
The SY88083L provides integrated 50Ω input and output impedances to optimize the high-speed signal paths and reduce component count. A TTL-compatible JAM input is provided to enable a SQUELCH function by feeding back the LOS or SD signal. The JAM input disables only the post amplifier output.
The SY88083L operates from a single +3.3V power supply, over temperatures ranging from –40°C to +85°C. |
| Linear | 2 | Active | The SY88147DL is a high-sensitivity limiting post amplifier designed for use in fiber-optic receivers. These devices connect to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88147DL quantizes these signals and outputs PECL level waveforms.
The SY88147DL operates from a single +3.3V power supply, over temperatures ranging from -40°C to +85°C. With its wide bandwidth and high gain, signals with data rates up to 1.25Gbps, and as small as 5mVPP, can be amplified to drive devices with PECL inputs.
The SY88147DL generates a high-gain loss-of-signal (LOS) open-collector TTL output. The LOS function has a high gain input stage for increased sensitivity. A programmable Loss-of-Signal level set pin (LOS LVL) sets the sensitivity of the input amplitude detection. LOS asserts high if the input amplitude falls below the threshold set by LOS LVL and de-asserts low otherwise. The enable bar input (/EN) de-asserts the true output signal without removing the input signal. The LOS output can be fed back to the /EN input to maintain output stability under a loss-of-signal condition. Typically 3.5dB LOS hysteresis is provided to prevent chattering. |
| Linear | 4 | Active | The SY88149NDL is a high-sensitivity, burst-mode capable limiting post amplifier designed for Optical Line Terminal (OLT) receiver applications. The SY88149NDL satisfies the strict timing restrictions of the GPON standards by providing ultra-fast Loss-of-Signal (LOS) or Signal-Detect (SD) output. Auto Reset and Manual Reset options are provided to control LOS/SD output timing. For increased flexibility, this device also includes an option to select between LOS or SD output. The device can be connected to burst-mode capable transimpedance amplifiers (TIAs) using AC or DC coupling.
The SY88149NDL generates a high-gain LOS or SD LVTTL output. A programmable LOS/SD level set pin (LOS/SDLVL) sets the sensitivity of the input amplitude detection. When LOS/SD SEL pin is left open or tied to Vcc, JAM is active high, SD is selected and asserts high if the input amplitude rises above the threshold sets by LOS/SDLVL and de-asserts low otherwise. When LOS/SD SEL pin is set low or tied to GND, JAM is active low, LOS is selected and asserts low if the input mplitude rises above the threshold sets by LOS/SDLVL and de-asserts high otherwise. The LOS/SD output can be fed back to the JAM input to maintain output stability under an invalid signal conditions. Typically, 4–5 dB SD hysteresis is provided to prevent chattering.
The SY88149NDL also features a selectable proprietary Noise Discriminator that aids by filtering out input signals that do not qualify as a 1.25Gbps GPON preamble signal in the initial startup phase. This feature minimizes false SD Asserts that can be triggered by random noise.
The SY88149NDL operates from a single +3.3V power supply, over temperatures ranging from –40°C to +85°C. With its wide bandwidth and high gain, signals up to 1.25Gbps and as small as 5mVpp can be amplified to drive devices with LVPECL inputs. |
| Power Management (PMIC) | 2 | Obsolete | |
| Integrated Circuits (ICs) | 1 | Obsolete | |
| Power Management (PMIC) | 1 | Obsolete | |
| Laser Drivers | 1 | Obsolete | |
| Integrated Circuits (ICs) | 1 | Obsolete | |
