Diodes Inc

CMOS & LVDS Ethernet Clock Generator

HiFlex™ High Performance Ethernet & Fibre Channel Clock Generator

PCIe 3.0 and Ethernet Clock Generator with 4 HCSL Outputs

3 Output LVPECL Networking Clock Generator

Next Generation HiFlex™ Ethernet Network Clock Generator

The PI6LC48S25B is an LC VCO based low phase noise design intended for 10GbE applications. Typical 10GbE usage assumes a 25MHz crystal input, while the PLL loop is used to generate the 156.25MHz and other Ethernet clock frequencies. An additional buffered crystal oscillator output is provided to serve as a low noise reference for other circuitry.

The PI6LC58S1101 is very low jitter clock generator target for applications that demand extremely low phase noise, such as 10GbE, 40GbE, 100GbE, and 400GbE. It uses Diodes' proprietary LC VCO-based PLL design to achieve an optimum combination of those popular networking clock frequencies and low phase noise performance along with high power supply noise rejection.

1:4 PCI Express® Clock Driver

The PI6ULS5V9306 is a dual bidirectional I2C-bus and SMBus voltage-level translator with an enable (EN) input. It is operational from 0.9V to 3.3V (VREF1) and 1.8V to 5V (VREF2).

The PI6ULS5V9511B is a hot-swappable I2 C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corrupting the data and clock buses. Control circuitry prevents the backplane from connecting to the card until a stop command or bus idle occurs on the backplane without bus contention on the card.When the connection is made, the PI6ULS5V9511B provides bidirectional buffering, which keeps the backplane and card capacitances isolated. The PI6ULS5V9511B rise-time accelerator circuitry allows the use of weaker DC pullup currents while still meetingrise-time requirements. The PI6ULS5V9511B incorporates a digital ENABLE input pin, which enables the device when asserted HIGH and forces the device into a low-currentmode when asserted LOW. The PI6ULS5V9511B also incorporates an open-drain READY output pin, which indicates that the backplane and card sides are connectedtogether (HIGH) or not (LOW). During insertion, the PI6ULS5V9511B SDA and SCL linesare pre-charged to 1.1V to minimize the current required to charge the parasitic capacitance of the chip.